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ORCIDBalwinder Raj
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2020 – today
- 2023
[j12]Parveen Kumar
, Balwinder Raj:
Design and simulation of junctionless nanowire tunnel field effect transistor for highly sensitive biosensor. Microelectron. J. 137: 105826 (2023)- 2022
- [j11]Parul Sharma, Balwinder Raj, Sandeep Singh Gill:
Spintronics Based Non-Volatile MRAM for Intelligent Systems: Memory for Intelligent Systems Design. Int. J. Semantic Web Inf. Syst. 18(1): 1-16 (2022) - 2021
- [j10]Manjit Kaur, Neena Gupta, Sanjeev Kumar, Balwinder Raj, Arun K. Singh:
Comparative radio-frequency and crosstalk analysis of carbon-based nano-interconnects. IET Circuits Devices Syst. 15(6): 493-503 (2021) - [j9]Tulika Chawla, Mamta Khosla, Balwinder Raj:
Design and simulation of triple metal double-gate germanium on insulator vertical tunnel field effect transistor. Microelectron. J. 114: 105125 (2021) - 2020
- [p2]Neeraj Jain, Balwinder Raj:
SOI FinFET for Computer Networks and Cyber Security Systems. Handbook of Computer Networks and Cyber Security 2020: 295-311
2010 – 2019
- 2019
- [j8]Candy Goyal, Jagpal Singh Ubhi, Balwinder Raj:
A low leakage TG-CNTFET-based inexact full adder for low power image processing applications. Int. J. Circuit Theory Appl. 47(9): 1446-1458 (2019) - [j7]Amandeep Singh, Mamta Khosla, Balwinder Raj:
Design and analysis of dynamically configurable electrostatic doped carbon nanotube tunnel FET. Microelectron. J. 85: 17-24 (2019) - [j6]Jeetendra Singh, Balwinder Raj:
Design and Investigation of 7T2M-NVSRAM With Enhanced Stability and Temperature Impact on Store/Restore Energy. IEEE Trans. Very Large Scale Integr. Syst. 27(6): 1322-1328 (2019) - [p1]Balwinder Raj, Jeetendra Singh, Santosh Kumar Vishvakarma, Shailesh Singh Chouhan:
IoT-Based Ambient Intelligence Microcontroller for Remote Temperature Monitoring. Guide to Ambient Intelligence in the IoT Environment 2019: 177-200 - 2018
- [j5]Gurmohan Singh, Balwinder Raj, Rakesh Kumar Sarin:
Fault-tolerant design and analysis of QCA-based circuits. IET Circuits Devices Syst. 12(5): 638-644 (2018) - 2017
- [j4]Gurmohan Singh, Rakesh Kumar Sarin, Balwinder Raj:
Design and analysis of area efficient QCA based reversible logic gates. Microprocess. Microsystems 52: 59-68 (2017) - 2016
- [j3]Sanjeev Kumar Sharma, Balwinder Raj, Mamta Khosla:
A Gaussian approach for analytical subthreshold current model of cylindrical nanowire FET with quantum mechanical effects. Microelectron. J. 53: 65-72 (2016) - [c9]Amandeep Singh, Mamta Khosla, Balwinder Raj:
CNTFET modeling and low power SRAM cell design. GCCE 2016: 1-4 - 2015
- [c8]Amandeep Singh, Mamta Khosla, Balwinder Raj:
Comparative analysis of carbon nanotube field effect transistors. GCCE 2015: 552-555 - [c7]Sanjeev Kumar Sharma, Balwinder Raj, Mamta Khosla:
Performance enhancement of junctionless nanowire FET with laterally graded channel doping and high-K spacers. GCCE 2015: 556-559 - [c6]Karmjit Singh Sandha, Balwinder Raj:
Thermally aware modeling and performance for MWCNT bundle as VLSI interconnects for high performance integrated circuits. GCCE 2015: 560-564 - [c5]Sunil Kumar, Balwinder Raj:
Modeling of DG-Tunnel FET for low power VLSI circuit design. IC3 2015: 455-458 - 2014
- [j2]Vijay Kumar Sharma, Manisha Pattanaik, Balwinder Raj:
PVT variations aware low leakage INDEP approach for nanoscale CMOS circuits. Microelectron. Reliab. 54(1): 90-99 (2014) - 2012
- [c4]Sushil Bhushan, Saurabh Khandelwal, Balwinder Raj:
Analyzing Different Mode FinFET Based Memory cell at different power supply for Leakage Reduction. BIC-TA (2) 2012: 89-100 - [c3]Shashikant Sharma, Manisha Pattanaik, Balwinder Raj:
Signal Stepping Based Multimode Multi-threshold CMOS Technique for Ground Bounce Noise Reduction in Static CMOS Adders. ISED 2012: 272-275 - 2011
- [j1]Balwinder Raj, Jatin Mitra, Deepak Kumar Bihani, V. Rangharajan, Ashok K. Saxena, Sudeb Dasgupta:
Process Variation Tolerant FinFET Based Robust Low Power SRAM Cell Design at 32 nm Technology. J. Low Power Electron. 7(2): 163-171 (2011) - [c2]Balwinder Raj, Ashok K. Saxena, Sudeb Dasgupta:
Quantum Mechanical Analytical Drain Current Modeling and Simulation for Double Gate FinFET Device Using Quasi Fermi Potential Approach. SocProS (2) 2011: 365-375 - 2010
- [c1]Balwinder Raj, Ashok K. Saxena, Sudeb Dasgupta:
Quantum Inversion Charge and Drain Current Analysis for Double Gate FinFET Device: Analytical Modeling and TCAD Simulation Approach. EMS 2010: 526-530
Coauthor Index
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