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2020 – today
- 2022
[j25]Ssu-Han Chen
, Yu-Wei Lai, Chung-Lun Kuo, Chieh-Yi Lo, Yu-Sung Lin, Yan-Rung Lin, Chih-Hsiang Kang, Chia-Chun Tsai:
A surface defect detection system for golden diamond pineapple based on CycleGAN and YOLOv4. J. King Saud Univ. Comput. Inf. Sci. 34(10 Part A): 8041-8053 (2022)- 2021
- [j24]Ssu-Han Chen, Chia-Chun Tsai:
SMD LED chips defect detection using a YOLOv3-dense model. Adv. Eng. Informatics 47: 101255 (2021) - 2020
- [c30]Chia-Chun Tsai, Chih-Chia Kuo, Yen-Lun Chen:
3D Hand Gesture Recognition for Drone Control in Unity*. CASE 2020: 985-988
2010 – 2019
- 2019
- [c29]Chia-Chun Tsai:
Performance Improvement for Stacked-Layer Data Bus Reconstruction on Complete Timing Period. ISOCC 2019: 52-53 - 2018
- [c28]Chia-Chun Tsai:
Embedded bus switches on 3D data bus for critical access time reduction. LASCAS 2018: 1-4 - 2017
- [c27]Chia-Chun Tsai:
Minimizing Critical Access Time for 3D Data Bus Based on Inserted Bus Switches and Repeaters. ISVLSI 2017: 140-145 - 2016
- [j23]Shin-Chi Lai, Wen-Ho Juang, Yueh-Shu Lee, Shin-Hao Chen, Ke-Horng Chen, Chia-Chun Tsai, Chiung-Hon Lee:
Hybrid Architecture Design for Calculating Variable-Length Fourier Transform. IEEE Trans. Circuits Syst. II Express Briefs 63-II(3): 279-283 (2016) - 2015
- [c26]Hong-Tzer Yang, Chiao-Tung Yang, Chia-Chun Tsai, Guan-Jhih Chen, Szu-Yao Chen:
Improved PSO based home energy management systems integrated with demand response in a smart grid. CEC 2015: 275-282 - 2013
- [c25]Trong-Yen Lee, Min-Jea Liu, Chia-Chen Fan, Chia-Chun Tsai, Haixia Wu:
Low Complexity Digit-Serial Multiplier over GF(2^m) Using Karatsuba Technology. CISIS 2013: 461-466 - [c24]Chia-Chun Tsai:
A reduced Li-Ion battery charger for portable applications. ICNC 2013: 1718-1722 - 2012
- [j22]Chia-Chun Tsai, Chung-Chieh Kuo, Feng-Tzu Hsu, Trong-Yen Lee:
Discharge-path-based antenna effect detection and fixing for X-architecture clock tree. Integr. 45(1): 76-90 (2012) - [j21]Kuan-Yu Lin, Hong-Ting Lin, Tsung-Yi Ho, Chia-Chun Tsai:
Load-balanced clock tree synthesis with adjustable delay buffer insertion for clock skew reduction in multiple dynamic supply voltage designs. ACM Trans. Design Autom. Electr. Syst. 17(3): 34:1-34:22 (2012) - [c23]Chia-Chun Tsai, Tsung-Ming Liu, Trong-Yen Lee:
Micro fuel cell power management circuit design for portable devices. FSKD 2012: 2493-2496 - 2011
- [j20]Chia-Chun Tsai, Chung-Chieh Kuo, Trong-Yen Lee:
Post-Routing Double-Via Insertion for X-Architecture Clock Tree Yield Improvement. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(2): 706-716 (2011) - [j19]Chung-Chieh Kuo, Chia-Chun Tsai, Trong-Yen Lee:
Pattern-matching-based X-architecture zero-skew clock tree construction with X-Flip technique and via delay consideration. Integr. 44(1): 87-101 (2011) - [j18]Chia-Chun Tsai, Sheng-Bin Dai, Trong-Yen Lee:
The RF Circuit Design of Power and Data Contactless Transmission for ISO/IEC 14443-2 Type B. J. Circuits Syst. Comput. 20(8): 1637-1658 (2011) - 2010
- [j17]Trong-Yen Lee, Che-Cheng Hu, Li-Wen Lai, Chia-Chun Tsai:
Hardware Context-Switch Methodology for Dynamically Partially Reconfigurable Systems. J. Inf. Sci. Eng. 26(4): 1289-1305 (2010) - [c22]Chia-Chun Tsai, Chung-Chieh Kuo, Lin-Jeng Gu, Trong-Yen Lee:
Double-via insertion enhanced X-architecture clock routing for reliability. ISCAS 2010: 3413-3416 - [c21]Chia-Chun Tsai, Chung-Chieh Kuo, Lin-Jeng Gu, Trong-Yen Lee:
Antenna Violation Avoidance/Fixing for X-clock routing. ISQED 2010: 508-514
2000 – 2009
- 2009
- [j16]Chia-Chun Tsai, Jan-Ou Wu, Trong-Yen Lee:
Maximal Delay Reduction for RLC-Based Multi-Source Multi-Sink Bus with Repeater Insertion. Circuits Syst. Signal Process. 28(6): 805-817 (2009) - [j15]Chia-Chun Tsai, Kai-Wei Hong, Trong-Yen Lee:
A Bisection-Based Power Reduction Design for CMOS Flash Analog-to-Digital converters. J. Circuits Syst. Comput. 18(5): 933-945 (2009) - [j14]Chia-Chun Tsai, Chin-Yen Lin, Yuh-Shyan Hwang, Trong-Yen Lee:
The Design of a Li-ion Battery Charger Based on Multimode LDO Technology. J. Circuits Syst. Comput. 18(5): 947-963 (2009) - 2008
- [j13]Chia-Chun Tsai, Jan-Ou Wu, Trong-Yen Lee:
GDME: Grey Relational Clustering Applied to a Clock Tree Construction with Zero Skew and Minimal Delay. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(1): 365-374 (2008) - [c20]Chia-Chun Tsai, Wei-Shi Lin, Jan-Ou Wu, Chung-Chieh Kuo, Trong-Yen Lee:
Layer assignment considering manufacturability in X-architecture clock tree. CIT 2008: 880-885 - [c19]Chia-Chun Tsai, Chung-Chieh Kuo, Jan-Ou Wu, Trong-Yen Lee, Rong-Shue Hsiao:
X-clock routing based on pattern matching. SoCC 2008: 357-360 - 2007
- [j12]Jan-Ou Wu, Chia-Chun Tsai, Chung-Chieh Kuo, Trong-Yen Lee:
Zero-Skew Driven Buffered RLC Clock Tree Construction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(3): 651-658 (2007) - [c18]Trong-Yen Lee, Yang-Hsin Fan, Yu-Min Cheng, Chia-Chun Tsai, Rong-Shue Hsiao:
Enhancement of Hardware-Software Partition for Embedded Multiprocessor FPGA Systems. IIH-MSP 2007: 19-22 - [c17]Trong-Yen Lee, Yang-Hsin Fan, Yu-Min Cheng, Chia-Chun Tsai, Rong-Shue Hsiao:
An Efficiently Hardware-Software Partitioning for Embedded Multiprocessor FPGA Systems. IMECS 2007: 346-351 - 2006
- [j11]Chia-Chun Tsai, Hann-Cheng Huang, Trong-Yen Lee, Wen-Ta Lee, Jan-Ou Wu:
Using Stack Reconstruction on RTL Orthogonal Scan Chain Design. J. Inf. Sci. Eng. 22(6): 1585-1599 (2006) - [c16]Chia-Chun Tsai, Jan-Ou Wu, Yu-Ting Shieh, Chung-Chieh Kuo, Trong-Yen Lee:
Tapping Point Numerical-Based Search for Exact Zero-Skew RLC Clock Tree Construction. APCCAS 2006: 812-815 - [c15]Chia-Chun Tsai, Jan-Ou Wu, Trong-Yen Lee, Rong-Shue Hsiao:
Propagation Delay Minimization on RLC-Based Bus with Repeater Insertion. APCCAS 2006: 1285-1288 - [c14]Trong-Yen Lee, Yang-Hsin Fan, Chia-Chun Tsai:
Reduction of RLC Tree Delay Using Bidirectional Buffer Repeater Insertion. ICICIC (2) 2006: 515-518 - [c13]Chun-Ying Lai, Shyh-Kang Jeng, Yao-Wen Chang, Chia-Chun Tsai:
Inductance extraction for general interconnect structures. ISCAS 2006 - [c12]Chia-Chun Tsai, Huang-Chi Chou, Trong-Yen Lee, Rong-Shue Hsiao:
A single chip image sensor embedded smooth spatial filter with A/D conversion. ISCAS 2006 - [c11]Chia-Chun Tsai, Jan-Ou Wu, Chien-Wen Kao, Trong-Yen Lee, Rong-Shue Hsiao:
Coupling aware RLC-based clock routings for crosstalk minimization. ISCAS 2006 - 2005
- [c10]Chia-Chun Tsai, Jan-Ou Wu, Chung-Chieh Kuo, Trong-Yen Lee, Wen-Ta Lee:
Zero-Skew Driven for RLC Clock Tree Construction in SoC. ICITA (1) 2005: 561-566 - [c9]Wen-Ta Lee, San-Ho Lin, Chia-Chun Tsai, Trong-Yen Lee, Yuh-Shyan Hwang:
A new low-power turbo decoder using HDA-DHDD stopping iteration. ISCAS (2) 2005: 1040-1043 - [c8]Yuh-Shyan Hwang, Lu-Po Liao, Chia-Chun Tsai, Wen-Ta Lee, Trong-Yen Lee, Jiann-Jong Chen:
A new CCII-based pipelined analog to digital converter. ISCAS (6) 2005: 6170-6173 - 2004
- [j10]Pei-Yung Hsiao, Yu-Chun Hsu, Wen-Ta Lee, Chia-Chun Tsai, Chia-Hao Lee:
An embedded analog spatial filter design of the current-mode CMOS image sensor. IEEE Trans. Consumer Electron. 50(3): 945-951 (2004) - [c7]Trong-Yen Lee, Yang-Hsin Fan, Tsung-Hsun Yang, Chia-Chun Tsai, Wen-Ta Lee, Yuh-Shyan Hwang:
RCGES: Retargetable Code Generation for Embedded Systems. ATVA 2004: 415-425 - 2000
- [j9]Cheng-Hsing Yang, Sao-Jie Chen, Jan-Ming Ho, Chia-Chun Tsai:
Efficient routability check algorithms for segmented channel routing. ACM Trans. Design Autom. Electr. Syst. 5(3): 735-747 (2000)
1990 – 1999
- 1999
- [c6]Jong-Sheng Cherng, Sao-Jie Chen, Chia-Chun Tsai, Jan-Ming Ho:
An Efficient Two-Level Partitioning Algorithm for VLSI Circuits. ASP-DAC 1999: 69-72 - [c5]Shuenn-Shi Chen, Jong-Jang Chen, Sao-Jie Chen, Chia-Chun Tsai:
An Automatic Router for the Pin Grid Array Package. ASP-DAC 1999: 133-136 - [c4]Shuenn-Shi Chen, Jong-Jang Chen, Sao-Jie Chen, Chia-Chun Tsai:
An Even Wiring Approach to the Ball Grid Array Package Routing. ICCD 1999: 303-306 - 1998
- [j8]Chia-Chun Tsai, Chwan-Ming Wang, Sao-Jie Chen:
NEWS: a net-even-wiring system for the routing on a multilayer PGA package. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(2): 182-189 (1998) - 1997
- [j7]Cheng-Hsing Yang, Chia-Chun Tsai, Jan-Ming Ho, Sao-Jie Chen:
Hmap: a fast mapper for EPGAs using extended GBDD hash tables. ACM Trans. Design Autom. Electr. Syst. 2(2): 135-150 (1997) - 1996
- [j6]Chia-Chun Tsai, De-Yu Kao, Chung-Kuan Cheng:
Performance driven bus buffer insertion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(4): 429-437 (1996) - 1995
- [c3]Chia-Chun Tsai, De-Yu Kao, Chung-Kuan Cheng, Ting-Ting Y. Lin:
Performance driven multiple-source bus synthesis using buffer insertion. ASP-DAC 1995 - 1994
- [j5]Chia-Chun Tsai, Sao-Jie Chen:
A Linear Time Algorithm for Planar Moat Routing. J. Inf. Sci. Eng. 10(1): 111-127 (1994) - 1992
- [j4]Chia-Chun Tsai, Sao-Jie Chen, Wu-Shiung Feng:
An H-V alternating router. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(8): 976-991 (1992) - [c2]Pei-Yung Hsiao, Chiao-Yi Lin, Chia-Chun Tsai:
Minimum Partition for the Space Region of VLSI Layout. VLSI Design 1992: 273-276 - 1991
- [j3]Pei-Yung Hsiao, S. F. Steven Chen, Chia-Chun Tsai, Wu-Shiung Feng:
A knowledge-based program for compacting mask layout of integrated circuits. Comput. Aided Des. 23(3): 223-231 (1991) - 1990
- [j2]Chia-Chun Tsai, Sao-Jie Chen, Wu-Shiung Feng:
Generalized terminal connectivity problem for multilayer layout scheme. Comput. Aided Des. 22(7): 423-433 (1990) - [j1]Chia-Chun Tsai, Sao-Jie Chen, Wu-Shiung Feng:
An H-V Tile-Expansion Router. J. Inf. Sci. Eng. 6(3): 173-189 (1990) - [c1]Pei-Yung Hsiao, Chia-Chun Tsai:
A new plane-sweep algorithm based on spatial data structure for overlapped rectangles in 2-D plane. COMPSAC 1990: 347-352
Coauthor Index
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