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ORCIDKonrad Lai
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2010 – 2019
- 2016
[i1]Yoongu Kim, Ross Daly, Jeremie S. Kim, Chris Fallin, Ji-Hye Lee, Donghyuk Lee, Chris Wilkerson, Konrad Lai, Onur Mutlu:
RowHammer: Reliability Analysis and Security Implications. CoRR abs/1603.00747 (2016)- 2014
- [c22]Tomas Karnagel, Roman Dementiev, Ravi Rajwar, Konrad Lai, Thomas Legler, Benjamin Schlegel, Wolfgang Lehner:
Improving in-memory database index performance with Intel® Transactional Synchronization Extensions. HPCA 2014: 476-487 - [c21]Jih-Kwon Peir, Shih-Chang Kevin Lai, Shih-Lien Lu, Jared Stark, Konrad Lai:
Author retrospective for bloom filtering cache misses for accurate data speculation and prefetching. ICS 25th Anniversary 2014: 65-67 - [c20]Yoongu Kim, Ross Daly, Jeremie S. Kim, Chris Fallin, Ji-Hye Lee, Donghyuk Lee, Chris Wilkerson, Konrad Lai, Onur Mutlu:
Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors. ISCA 2014: 361-372 - 2013
- [c19]Richard M. Yoo, Christopher J. Hughes
, Konrad Lai, Ravi Rajwar:
Performance evaluation of Intel® transactional synchronization extensions for high-performance computing. SC 2013: 19:1-19:11
2000 – 2009
- 2006
- [j6]Amit Gandhi, Haitham Akkary, Ravi Rajwar, Srikanth T. Srinivasan, Konrad Lai:
Scalable Load and Store Processing in Latency-Tolerant Processors. IEEE Micro 26(1): 30-39 (2006) - 2005
- [j5]Ayose Falcón, Jared Stark, Alex Ramírez, Konrad K. Lai, Mateo Valero:
Better Branch Prediction Through Prophet/Critic Hybrids. IEEE Micro 25(1): 80-89 (2005) - [c18]Dinesh Somasekhar, Shih-Lien Lu, Bradley A. Bloechel, Greg Dermer, Konrad Lai, Sjeljar Borkar, Vivek De:
A 10Mbit, 15GBytes/sec bandwidth 1T DRAM chip with planar MOS storage capacitor in an unmodified 150nm logic process for high-density on-chip memory applications. ESSCIRC 2005: 355-358 - [c17]Amit Gandhi, Haitham Akkary, Ravi Rajwar, Srikanth T. Srinivasan, Konrad K. Lai:
Scalable Load and Store Processing in Latency Tolerant Processors. ISCA 2005: 446-457 - [c16]Ravi Rajwar, Maurice Herlihy, Konrad K. Lai:
Virtualizing Transactional Memory. ISCA 2005: 494-505 - [c15]Saisanthosh Balakrishnan, Ravi Rajwar, Michael Upton, Konrad K. Lai:
The Impact of Performance Asymmetry in Emerging Multicore Architectures. ISCA 2005: 506-517 - 2004
- [j4]Lu Peng, Jih-Kwon Peir, Konrad Lai:
A New Address-Free Memory Hierarchy Layer for Zero-Cycle Load. J. Instr. Level Parallelism 6 (2004) - [c14]Lu Peng, Jih-Kwon Peir, Konrad Lai:
Signature Buffer: Bridging Performance Gap between Registers and Caches. HPCA 2004: 164-175 - [c13]Srikanth T. Srinivasan, Haitham Akkary, Tom Holman, Konrad Lai:
A Minimal Dual-Core Speculative Multi-Threading Architecture. ICCD 2004: 360-367 - [c12]Ayose Falcón, Jared Stark, Alex Ramírez, Konrad Lai, Mateo Valero:
Prophet/Critic Hybrid Branch Prediction. ISCA 2004: 250-263 - 2003
- [j3]Lu Peng, Jih-Kwon Peir, Qianrong Ma, Konrad Lai:
Address-free memory access based on program syntax correlation of loads and stores. IEEE Trans. Very Large Scale Integr. Syst. 11(3): 314-324 (2003) - [c11]Shih-Lien Lu, Konrad Lai:
Implementation of HW$im - A Real-Time Configurable Cache Simulator. FPL 2003: 638-647 - [c10]Haitham Akkary, Srikanth T. Srinivasan, Konrad Lai:
Recycling waste: exploiting wrong-path execution to improve branch prediction. ICS 2003: 12-21 - 2002
- [c9]Jih-Kwon Peir, Shih-Chang Lai, Shih-Lien Lu, Jared Stark, Konrad Lai:
Bloom filtering cache misses for accurate data speculation and prefetching. ICS 2002: 189-198 - [c8]Steven Hsu, Shih-Lien Lu, Shih-Chang Lai, Ram Krishnamurthy, Konrad Lai:
Dynamic addressing memory arrays with physical locality. MICRO 2002: 161-170 - 2001
- [j2]Ronny Ronen, Avi Mendelson, Konrad Lai, Shih-Lien Lu, Fred J. Pollack, John Paul Shen:
Coming challenges in microarchitecture and architecture. Proc. IEEE 89(3): 325-340 (2001) - [c7]Qianrong Ma, Jih-Kwon Peir, Lu Peng, Konrad Lai:
Symbolic Cache: Fast Memory Access Based on Program Syntax Correlation of Loads and Stores. ICCD 2001: 54-61 - [c6]Byung-Kwon Chung, Jinsuo Zhang, Jih-Kwon Peir, Shih-Chang Lai, Konrad Lai:
Direct load: dependence-linked dataflow resolution of load address and cache coordinate. MICRO 2001: 76-87
1990 – 1999
- 1992
- [c5]Wen-Hann Wang, Jim Quinlan, Konrad Lai:
Revisit the case for direct-mapped chaches: a case for two-way set-associative level-two caches. ISCA 1992: 437 - 1990
- [c4]Fred J. Pollack, Dave Johnson, Dave Carson, Ron Ebersole, Vittal Kini, Konrad Lai, Bernie Silvernail, Steve Stacey:
A VLSI-intensive fault-tolerant computer architecture. Compcon 1990: 134-142
1980 – 1989
- 1988
- [c3]Glenn Hinton, Konrad Lai, Randy Steck:
Microarchitecture of the 80960 high-integration processors. ICCD 1988: 362-365 - 1983
- [j1]George W. Cox, William M. Corwin, Konrad K. Lai, Fred J. Pollack:
Interprocess Communication and Processor Dispatching on the Intel 432. ACM Trans. Comput. Syst. 1(1): 45-66 (1983) - 1982
- [c2]Fred J. Pollack, George W. Cox, Dan W. Hammerstrom, Kevin C. Kahn, Konrad K. Lai, Justin R. Rattner:
Supporting Ada Memory Management in the iAPX-432. ASPLOS 1982: 117-131 - 1981
- [c1]George W. Cox, William M. Corwin, Konrad K. Lai, Fred J. Pollack:
A Unified Model and Implementation for Interprocess Communication in a Multiprocessor Environment. SOSP 1981: 125-126
Coauthor Index
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