"A 32 Gb/s ADC-Based PAM-4 Receiver with 2-bit/Stage SAR ADC and ..."

Shiva Kiran et al. (2019)

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DOI: 10.1109/CICC.2019.8780283

access: closed

type: Conference or Workshop Paper

metadata version: 2022-03-31

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Shiva Kiran, Shengchang Cai, Ying Luo, Sebastian Hoyos, Samuel Palermo:
A 32 Gb/s ADC-Based PAM-4 Receiver with 2-bit/Stage SAR ADC and Partially-Unrolled DFE. CICC 2019: 1-4

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