"An optimal transistor-chaining algorithm for CMOS cell layout."

Chi-Yi Hwang et al. (1989)

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DOI: 10.1109/ICCAD.1989.76967

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  - https://dblp.org/rec/conf/iccad/HwangHLH89
Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu:
An optimal transistor-chaining algorithm for CMOS cell layout. ICCAD 1989: 344-347

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