"Approximate Logic Synthesis in the Loop for Designing Low-Power Neural ..."

Yifan Qian et al. (2021)

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DOI: 10.1109/ISCAS51556.2021.9401451

access: closed

type: Conference or Workshop Paper

metadata version: 2024-06-03

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Yifan Qian, Chang Meng, Yawen Zhang, Weikang Qian, Runsheng Wang, Ru Huang:
Approximate Logic Synthesis in the Loop for Designing Low-Power Neural Network Accelerator. ISCAS 2021: 1-5

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