"Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based ..."

Alexandre M. Amory et al. (2007)

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DOI: —

access: open

type: Informal or Other Publication

metadata version: 2018-08-13

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  - electronic edition @ arxiv.org (open access)
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  dblp key:
  - journals/corr/abs-0710-4795
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  persistent URL:
  - https://dblp.org/rec/journals/corr/abs-0710-4795
Alexandre M. Amory, Marcelo Lubaszewski, Fernando Gehm Moraes, Edson I. Moreno:
Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture. CoRR abs/0710.4795 (2007)

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