Shielded piezoresistive cantilever probes for nanoscale topography and electrical imaging

Microwave impedance microscopy (MIM) is now established as an indispensable tool to study nanoscale dielectric and conductive properties of materials [1]. As shown in figure 1, GHz microwave signals are guided to a conductive tip and interact with the materials beneath the tip apex. The reflected signals, which contain local electrical information of the sample, are amplified and demodulated to form MIM-Im (imaginary component) and MIM-Re (real component) images. This technique enables direct visualization of the nanoscale complex permittivity [2, 3] under ambient [4] or low temperatures [5]; it has already found application in the study of fundamental problems in electron physics [6–8] and material science [9].

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Height control feedback is essential for scanning probe microscopy (SPM) because it regulates the tip–sample interaction, prevents tip crash, and provides topographic information of the sample surface. The room temperature MIM is usually implemented on a commercial atomic force microscope (AFM) to take advantage of the conventional laser beam feedback [1–4, 9]. A major drawback of laser feedback is the influence of stray light on photo-sensitive materials. In addition, height control feedback inside cryogenic chambers is not trivial due to limited setup space. Here, we implement a non-optical feedback scheme to provide topographic information during the MIM measurement and to minimize tip crashes, thus preserving tip sharpness.

Piezoresistive sensing is an established feedback mechanism for contact mode SPM [10]. However, integration of a piezoresistor on MIM probes is a challenging task. First, the fabrication of a piezoresistive element should be compatible with batch process of sharp conductive tip apex, which sets the MIM spatial resolution [4]. Second, a low-resistance metallic path from the bonding pad (for signal input/output) to the tip apex is needed to minimize the loss. The background capacitance between this signal line and the ground should also be kept small for better electrical sensitivity. Third, the signal line should be electrically shielded to reduce the stray fields and noise pickup. In other words, the center conductor should be surrounded by dielectrics and then shield metals. Finally, such a sandwich structure with stacking metal/dielectric layers is highly susceptible to bimorph bending [11]. Thus, the stresses and thermal expansions of different layers must be balanced such that the cantilever remains straight over the variable temperature range. The MIM probes produced so far show good electrical and mechanical performance but no piezoresistive element [12, 13]. We previously reported piezoresistive probes with doped n-type silicon piezoresistors on p-type silicon device layer of SOI wafers. Those probes exhibited a vertical displacement resolution of 3.5 nm at 10 kHz bandwidth. The un-optimized center conductor and dielectric layers resulted in large resistance (32 Ω) and capacitance (9.5 pF), which were unfortunately too large for the MIM [14].

In this work, we report novel batch-processed low impedance, well-shielded piezoresistive cantilever probes. SOI wafers with low resistive n-type silicon are used as starting material. Piezoresistors fabricated by thinning the n-type silicon device layer are integrated on plasma enhanced chemical vapor deposition (PECVD) Si₃N₄ cantilever to detect the deformation due to tip–sample contact force. Capsulated by SiO₂, the piezoresistors show low noise and the height resolution is 2 nm in a 10 kHz band, which enables high quality topographic imaging. A shielded aluminum center conductor connects the sharp silicon tip to a bond pad on the die handle. With the optimized center conductor and dielectric layers, the resistance of the center conductor is less than 5 Ω and the capacitance between the center conductor and outer shield is 1.7 pF. These low resistance and capacitance values are critical for high sensitivity MIM imaging. The optimized cantilever structure also ensures the cantilever to be flat at variety temperatures. Using these new piezoresistive microwave probes, high quality topographic and MIM images are simultaneously obtained under both ambient and cryogenic temperatures.

A schematic of the designed piezoresistive cantilever microwave probe is shown in figure 1. The main body of the cantilever is made of PECVD Si₃N₄. A heavily doped n-type silicon tip is integrated on the cantilever free end. The aluminum center conductor connects the tip to a wire bond pad to guide microwave signals to and from the tip. The cantilever front side (tip side) is covered by an Al shield layer, which is electrically grounded in the microwave measurements to suppress noise pickup. Two on-chip heavily doped Si piezoresistors, one on the cantilever and the other as a background reference, are connected into a Wheatstone bridge circuit for the detection of cantilever deformation that provides feedback to the z-scanner.

In the probe design, we minimized both the series resistance (R_s) of the center conductor and its capacitance (C_tip) to ground. The small R_s decreases the loss in the signal line and increases the sensitivity. In our case, the thick center conductor (1 µm Al) and optimized conductor path width (6 µm on the cantilever and 15 µm on the chip) keep the R_s small. In MIM, the tip–sample interaction is essentially a tiny modulation to the tip capacitance. We have used a sufficiently thick dielectric (1.5 µm Si₃N₄) and optimized conductor path width to minimize C_tip.

For a cantilever with multiple layers and different materials, it is important to balance the mechanical and thermal stresses to keep it straight at variable temperatures. In our design, Al metal and Si₃N₄ with low stress are used to minimize the internal stress at the room temperature. The shape and thickness of Al center conductor and Si₃N₄ dielectric layers are optimized for small resistance and capacitance. The only tunable layer is the metal shield. We used COMSOL finite element modeling (FEM) simulation to optimize the shield metal thickness. A 100 nm Al shield was chosen to obtain low thermal stress and with conformal electrical shielding capability. Figure 2 shows the simulated displacement of cantilever when the temperature drops from 20 °C to −196 °C. The cantilever free end only moves 7.5 µm, which is small enough to meet our requirements for low temperature scanning.

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The probes are fabricated on (1 0 0) SOI wafers with an 8 µm device layer, 2 µm buried silicon dioxide (BOX), and 400 µm handle layer. The device layer and handle wafer are heavily doped n-type silicon with a resistivity of 0.001–0.0015 Ω•cm for low resistance and good Ohmic contact with Al. During the process, the wafers were rotated 45° to make the piezoresistors along 〈1 0 0〉 crystal direction and maximize the piezoresistive coefficient in n-type silicon [15].

The detailed fabrication processes are shown in figure 3. The starting material was SOI wafer (figure 3(a)). A 100 nm thermal SiO₂ was grown on the wafer and patterned with 15 µm × 15 µm square tip etch masks. The wafer was then etched in 45% KOH at 60 °C for about 30 min. Tall tips of 7 µm with uniform height were created by undercutting the oxide mask, with about 1 µm left in the remaining device layer (figure 3(b)). A second 100 nm SiO₂ layer was grown in a wet atmosphere at 950 °C to sharpen the tip apex. After patterning the SiO₂, the wafer was again etched in 45% KOH at 60 °C for about 5 min to form a stage around the tip and the piezoresistors. The thickness of the stage and piezoresistor is in the range of 0.5 to 1.5 µm due to the inhomogeneity of SOI device layer (figure 3(c)). The tips were further sharpened by growing a 200 nm thick oxide at 950 °C in a wet atmosphere (figure 3(d)), followed by the removal of the oxide on piezoresistor contact holes and the stage by buffered oxide etch (BOE). The oxide on the tip was kept to protect the apex during the following processes (figure 3(e)). A layer of 1 µm Al was deposited on the wafer and patterned into the center conductor, which connects the tip stage and bond pad on the chip to guide microwave signals. The dummy trace on the other side of the cantilever balances the lateral structure. Electrodes for the piezoresistors were also formed at the same process (figure 3(f)). A dielectric layer of 1.5 µm PECVD Si₃N₄ was then deposited and patterned as the cantilever body by reactive-ion etching (figure 3(g)). The front layer of 0.1 µm Al served as the shield was sputtered and patterned (figure 3(h)). Note that the via–hole through the dielectric layer is to electrically ground the dummy wire to the shield, which is shown in the top views of figures 3(f)–(h). We then removed the Al and SiO₂ on the tip to expose the tip apex by Al etchant and pad etchant (SiO₂ etch rate = 35 nm min⁻¹), respectively. To release the cantilever probes, we spin coated both sides of the wafers with 7 µm photoresist, then patterned the back side and etched away the silicon underneath the cantilever by deep reactive ion etching (DRIE). The BOX layer was removed by pad etchant to complete the cantilever release (figure 3(i)). Finally, the probes are annealed in forming gas at 450 °C for 30 min to form Ohmic contacts between the heavy doped silicon and the Al center conductor. In the fabrication, 1 µm spin-coated photoresist was used during the patterning of tip etch masks (figure 3(b)) and 7 µm spin-coated photoresist was used after the tip formation by KOH etching, which created 7 µm steps on the wafer (figure 3(c)).

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As shown in figure 4, hundreds of probes are batch fabricated on a 4 inch wafer (figure 4(a)). The dimensions are 3.4 mm ×1.6 mm for the chips and 300 µm ×75 µm for the cantilever. A scanning electron micrograph (SEM) in figure 4(b) displays active and reference cantilevers, as well as the bond pad. Figure 4(c) is a full view of the MIM cantilever and figure 4(d) shows the piezoresistor at its root. Close-up views of the tip in figures 4(e) and (f) demonstrate a sharp tip apex with a diameter less than 50 nm. The reference cantilever has the same structure as the sensing cantilever except that it has no tip on the free end.

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The two on-chip piezoresistors were connected with two metal film resistors to form a Wheatstone bridge configuration. A 1 V dc bias was applied on the bridge and the output was amplified with an instrumentation amplifier, which has the bandwidth of 800 kHz and a very low noise that can be negligible during the testing. The amplified signal was then sent to the control circuit to provide feedback to the z-scanner. The piezoresistor on the reference cantilever balances the environment induced fluctuation and drift. The low frequency noise spectrum was measured by a signal analyzer HP3562A and the results are shown in figure 5. Bandwidth of 1 Hz to 10 kHz was chosen to match the AFM feedback loop bandwidth, which generally is around 10 kHz. The integrated noise from 1 Hz to 10 kHz at 1 V dc bias is:

$$\begin{equation} V_{{\rm noise}} = \sqrt {\mathop \int_{f = 1\;{\rm Hz}}^{10000\;{\rm Hz}} [ {V( f )} ]^2\, {\rm d}f} = 428\;{\rm nV}\end{equation} \tag{ 1 }$$

where V(f) is the measured noise spectrum density in figure 5.

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To measure the displacement sensitivity, the probe was mounted on a Park XE-70 AFM system to approach a hard sample surface. The amplified bridge output versus AFM z-scanner displacement was measured, which shows a typical approach–retract curve (figure 6). The slope gives a sensitivity of 2.2 × 10⁴ V m⁻¹ with an amplifier gain of 100 and 1 V dc bias. The vertical resolution of the piezoresistive probe for a bandwidth of 10 kHz can be calculated:

$$\begin{equation} {\rm Res} = \frac{V_{\rm noise}}{\rm Sensitivity} = 2\;{\rm nm}\end{equation} \tag{ 2 }$$

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Thanks to the optimized parameters of Al center conductor and Si₃N₄ dielectric, our probes show small R_s (measured less than 5 Ω) and C_tip (measured about 1.7 pF), much better than the doped Si trace in other reports [13]. The optimized cantilever structure not only minimizes the noise pickup and the topographic artifact, but also balances the stresses to keep the cantilever straight under variable temperatures. It is difficult to optically observe the cantilever shape at low temperature due to the complicated cryogenic system. So we heated the cantilever to be 127 °C to prove it. As shown in figure 7, the cantilever is reasonably flat at the room temperature and maintains its shape when being heated to 127 °C.

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Results of simultaneous topographic and MIM imaging at the room temperature are shown in figure 8. The sample contains 10 nm tall Al dots on a silicon substrate with 100 nm SiO₂. In the scanning, we used piezoresistive bridge output as feedback to control the z-scanner displacement and the topography is obtained from the z-scanner position. The topography obtained by piezoresistive feedback (figure 8(a)) has the same quality as that obtained with traditional laser feedback (figure 8(b)). The MIM images (figures 8(c) and (d)) were simultaneously recorded by microwave electronics, showing clear MIM-Im contrast between the conducting Al and insulating SiO₂. Details about the analysis of MIM images can be found in [2–4, 13].

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Figure 9 shows the results at cryogenic temperature (−196 °C). The scanning was done in Janis cryogenic cryostat based MIM setup, which is the sample as that in [4] except for the piezoresistive probe. The tip, sample as well as the scanners were placed in a vacuum tube with helium exchange gas. Then the tube was immersed in liquid nitrogen to reach −196 °C. The sample is a 100 nm SiO₂/Si wafer, with the SiO₂ etched in a stripe pattern. Here the topography, shown in figure 9(a), was directly recorded from the piezoresistive output. The MIM-Im contrast reflects the tip–sample capacitance change between the 100 nm SiO₂ layer and native oxide on the etched regions. No contrast is observed in the MIM-Re image, as expected for the insulating SiO₂ surface.

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We have demonstrated piezoresistive cantilever MIM probes integrated with low impedance, electrical shield and sharp tips for simultaneously topographical and electrical SPM. The piezoresistive displacement resolution is 2 nm in a band from 1 Hz to 10 kHz. The resistance of the center conductor is less than 5 Ω and the tip-to-ground capacitance is 1.7 pF. The small resistance and capacitance, as well as the shielded structure ensure the excellent electrical performance. The probes show good piezoresistive topographic and MIM capability at both room and cryogenic temperatures. These novel piezoresistive probes broaden MIM applications in scientific and engineering studies of new materials and electronic devices.

Fabrication work was performed in part at the Stanford Nanofabrication Facility (a member of the National Nanotechnology Infrastructure Network) supported by the NSF under grant ECS-9731293, its lab members, and the industrial members of the Stanford Center for Integrated Systems. This work is supported by National Science Foundation (NSF) under grant no DMR-130573, Center of Probing the Nanoscale (CPN) grant no PHY-0425897 and the Gordon and Betty Moore Foundation through grant GBMF3133 to ZXS. The authors would like to thank the Stanford Nanofabrication Facility staff for their advice and help.