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A New Low Power Test Pattern Generator for BIST Architecture Kicheol KIM Dongsub SONG Incheol KIM Sungho KANG Publication IEICE TRANSACTIONS on Electronics Vol.E88-C No.10 pp.2037-2038 Publication Date: 2005/10/01 Online ISSN: DOI: 10.1093/ietele/e88-c.10.2037 Print ISSN: 0916-8516 Type of Manuscript: LETTER Category: Semiconductor Materials and Devices Keyword: low power BIST, low power test pattern generator, Full Text: PDF(279.9KB)>>
Summary: A new low power test pattern generator (TPG) which can effectively reduce the average power consumption during test application is developed. The new TPG reduces the weighted switching activity (WSA) of the circuit under test (CUT) by suppressing transitions at some primary inputs which make many transitions. Moreover, the new TPG does not lose fault coverage. Experimental results on the ISCAS benchmark circuits show that average power reduction can be achieved up to 33.8% while achieving high fault coverage. | |||||
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