A dual model node based optimization algorithm for simultaneous escape routing in PCBs

Related work

PCBs are widely used for the modern age electric circuits fabrication. The design of a PCB plays a vital role in the performance of electric circuits. The ever evolving technology has not only reduced the size of ICs that are to be placed on the PCBs but has also increased the pin count of ICs. This makes the process of manual PCB routing a very hectic task and demands automated PCB routing. The problems that are to be solved in the PCB routing are escape routing, area routing, length matching, and number of layers that are to be used. Many studies in the literature have addressed these routing problems related to the PCBs.

Some studies have proposed the heuristics algorithms to obtain a length matching routing (Zhang et al., 2015b) and others have used differential pair escape (Li et al., 2012, 2019), single signal escape routing (Wu & Wong, 2013) or both (Wang et al., 2014) for escape routing along with addressing the length matching problem. The most notable technique used for the PCB routing is optimization. There are various studies in literature that have mapped different PCB routing problems to the optimization problem such as longest common interval sequence problem (Kong et al., 2007), multi-layer assignment problem (Yan, Kong & Wong, 2009), network flow problem (Sattar & Ignjatovic, 2016), pin assignment and escape routing problem (Lei & Mak, 2015), and maximum disjoint set of boundary rectangles problem for bus routing (Ahmadinejad & Zarrabi-Zadeh, 2016). A recent study has proposed a routing method that is based upon maze and it uses a hierarchical scheme for bus routing and the proposed method uses a rip-up and re-route technique as well in order to improve the efficiency (Chen et al., 2019).

There are different problems to be solved in the PCB routing as discussed earlier and one of the most important problem among these is the escape routing where the pins from inside of an IC are to be escaped to the boundary of IC. Many studies in the literature have proposed solutions for escape routing problem among which some have considered single layer (Lei & Mak, 2015) in the PCB while, multiple layers (Bayless, Hoos & Hu, 2016, Zhang et al., 2015a) have also been considered. There are studies that only consider escape routing (McDaniel, Grissom & Brisk, 2014) while, there are some studies which consider other problems like length matching (Zhang et al., 2015b, Yan, 2015, Chang, Wen & Chang, 2019) along with the escape routing as well. Some have used staggered pin array (Ho, Lee & Chang, 2013; Ho et al., 2013) while others have used grid pin array (Jiao & Dong, 2016) as well. Apart from electrical circuits, escape routing is also used for designing micro-fluid biochips PCBs (McDaniel et al., 2016). The most widely used technique for the solution of escape routing is the optimization theory and it has been used for the past many years and also been employed by the current studies (Katagiri et al., 2016; Serrano et al., 2016; Ahmadinejad & Zarrabi-Zadeh, 2016).

The problem of escape routing is not the only problem to which the optimization theory provides solution to. The optimization theory has also been deployed by several other fields in which routing of packets in the wireless networks is the most prominent one. There is a recent study in which optimization theory is used in the wireless sensor networks (WSNs) for the smart power grids (Kurt et al., 2017). The authors have proposed a novel mixed integer program with the objective function of maximizing the lifetime of a WSN through joint optimization of data packet size and the transmission power level. Apart from wireless sensor networks, the rechargeable sensor networks also face the problem of energy harvesting. Optimization techniques have also been used in these types of networks in order to jointly optimize the data sensing and transmission and achieve a balanced energy allocation scheme (Zhang, He & Chen, 2015). The optimization theory is also used in addressing the power optimization issues of the communication systems to fulfill the different demands of different message types regarding the QoS, length of packet and transmission rates ?. The optimization theory has also been used to increase the efficiency of the urban rail timetable (Xue et al., 2019). The authors propose a nonlinear integer program in order to obtain a rail timetable which is efficient. The model is then simplified into an integer program with a single objective. A 9.5% reduction in wasted capacity is achieved through the use of a genetic algorithm in this study.

The application of optimization theory is not only limited to the fields of communication and networking but it is also been used in the vehicle routing problem (Thongkham & Kaewman, 2019), network reconfiguration for Distribution Systems (Guo et al., 2020), microgrid systems (Wu et al., 2019), distributed energy resource allocation in virtual power plants (Ko & Joo, 2020), control of humanoid robots Tedrake (2017), smart grid ecosystem (Koutsopoulos, Papaioannou & Hatzi, 2016) and Computation of the Centroidal Voronoi Tessellations (CVT) that is widely used in the computer graphics (Liu et al., 2016). Ozdal & Wong (2004) and Ozdal & Wong (2006) can be regarded as the initial work on SER as they consider two pin arrays simultaneously and minimize the net ordering mismatch. There are some studies in the literature that have proposed a simultaneous pin assignment Xiang, Tang & Wong (2001), Wang, Lai & Liu (1991). Ozdal & Wong (2004, 2006) propose a methodology to escape the pins to boundaries in such a way that crossings are minimized in the intermediate area. Polynomial time algorithm is used for smaller problems and randomized algorithm approach is proposed for routing in the case of larger examples.

It is stated that the routing resources available inside the pin array are less as compared to the routing resources that are available in the intermediate area. This is because of the reason that pins are densly packed inside the pin array. Also, using vias is not allowed within the pin array and the routing inside pin array must be free from conflicts and overlapping. Via usage is allowed in the intermediate area as opposed to the pin arrays. The problem is formulated as to find out best escape routing solution within the pin array so that the conflicts in intermediate area are minimized. There are two phases to solve the problem. In the first phase, a single layer is taken at a time and maximum possible non conflicting routes are packed on that layer. The conflicted routes are routed on the next layer and hence, escape routing is completed in this manner (Ozdal & Wong, 2004, 2006).

In the second phase of problem solution, a congestion based net-by-net approach is used for routing in the intermediate area. Routing conflicts are allowed at the beginning and optimal solution is found by rip-up and re-route approach. The ripping up of routes that are formed in the first phase is discouraged and in order to find a conflict free route for all pins which is obtained eventually. A number of routing patterns are defined for each net and a polynomial time algorithm is proposed in order to choose the best possible combination from all the given possible routing patterns. The results for different industrial data sets are obtained which show that optimal routes are increased and time required for routing is decreased as compared to other algorithms. Although it is a good approach, but 99.9% routability is not achieved in the escape routing problem and too much time is taken in the area routing problem (Ozdal & Wong, 2004, 2006).

Same authors propose an algorithm in Ozdal, Wong & Honsinger (2007) to solve the escape routing problems in multiple components simultaneously. Some design constraints have also been considered along with routing. The escape patterns considered in this algorithm are more generalized in comparison to the algorithm proposed in their previous research (Ozdal & Wong, 2004). The objective is to minimize the crossover in intermediate area, hence less via usage. For smaller circuits, results given by their proposed randomized algorithm are within 3% of optimal solution, but optimal solution is not achieved in the case of larger circuits due to time complexity. They have also assumed fixed pattern generation which can be successful in the case of smaller circuits where components are well aligned, but complex problems cannot be solved easily by using these approaches (Ozdal & Wong, 2004; Ozdal, Wong & Honsinger, 2007). B-Escape (Luo et al., 2010; Luo et al., 2011) solves this issue by removing the consumed routing area by a pin and shrinking the boundary. B-Escape reduced the time complexity and also increased the routability but, it can cause pin blockage when certain area is removed and boundaries are shrunk. Also, the time taken to solve most of the problems is still greater than 1 min which is not optimal and needs to be reduced further than that (Luo et al., 2010; Luo et al., 2011).

In addition to the above mentioned studies, other techniques have also been used in the literature for SER solution and one of them is negotiated congestion based routing scheme (Qiang, Yan & Wong, 2010). Negotiated congestion based routing already has its application in FPGA routing. However, it is not being used for solving SER problem. A negotiated congestion based router is proposed which applies the negotiated congestion routing scheme on an underlying routing graph. In negotiated congestion approach, all pins are forced to negotiate for a resource which is the routing space in case of PCB. The pin needing most resources is determined. Some resources are shared between pins and these pins are routed again and again iteratively till no resources are shared among the pins. Results have been compared with Cadence PCB router Allegro and it was found that proposed router is able to achieve 99.9% routability in case of such circuits which are not routed completely by the Allegro. Time consumption is also less, but the issue is that there are some examples in which the proposed router is not able to achieve 99.9% routability while Allegro is able to achieve. It is proposed that the router should be used in collaboration with Allegro so that all the problems can be solved.

There is another research (Yan, Sung & Chen, 2011) which uses ordered escape routing in order to solve the SER problem. The SER problem is solved by determining the net order. A bipartite graph is created on the basis of location of escape pins and transformation of net numbers is done. After doing SER, the net numbers are recovered. Basically, the orders of escape nets are found along the boundary in such a way that there is no crossover in the intermediate area. This approach achieves 99.9% routability along with reduction in time consumption, but the achieved net order is not routable in all cases. This approach can fail in some specific cases where the ordering proposed by the approach is not routable. Quite recently, net ordering has been incorporated with the SER through proposal of a novel net ordering algorithm in order to reduce the running time (Sattar et al., 2017). Recently, we have proposed the solution to this problem through a network flow approach (Ali, Zeeshan & Naveed, 2017). We proposed the solution to this problem through a network flow approach where we introduced two different models; one is based on the links and called Link based routing, while the other is based on nodes and is called Nodes based routing. They are introduced to solve SER problem in PCBs through optimization techniques. The models were successful in routing over small grids but consumed too much time when run over the larger grids.

As per our findings, the SER has been explored by these studies and they have provided some good solutions with various limitations. There are some major issues that still seem to be unresolved and they include fixed pattern generation and time complexity. Most of these studies are unable to solve problems like pin blockage and resource under utilization. The studies have used randomized approaches and heuristic algorithms and optimal solutions are not provided. In this study, we provide an optimal solution having a time complexity of under a minute along with 99.9% routability for the problem of SER in the PCBs.

Problem formulation

The number of pins in an IC has been increased considerably and the footprint of an IC has shrunk in recent years making the escape routing problem very difficult. The studies in literature have used randomized approaches and heuristic algorithms to solve the escape routing problem which have not been able to reduce time complexity, achieve 99.9% routability, and provide optimal solutions. The problem of SER has been solved in this study through proposal of an optimal algorithm that not only achieves the 99.9% routability but also consumes very less time and memory to find out the optimal solution.

The problem of SER basically boils down to connection of pins of two components. There are many components on a PCB but there are also many layers available for routing of these components. We solve this problem by taking two components at a time and producing the best possible routing solution for them. The routing of two components can be generalized for multiple components. The basic problem is to escape the pins from inside the pin array of two components and then to connect them by using area routing. As the size of a pin array is very small and routing resources are very less inside the pin array so vias cannot be used inside the pin array and all the pins inside pin array must be routed on a same layer. Once these pins are escaped onto the boundary, different layers can be used for their routing to avoid the conflicts in area routing.

The problem is formulated such that these conflicts in the intermediate area are minimized and least possible vias are used. The problem can be understood with the help of illustrations. Three ICs can be seen in the Fig. 1, in which some pins are represented with lines inside a hollow circle. Different patterns of the lines inside hollow circles can be seen. The pins represented by same patterned circles have to be connected with each other. The pins represented by the simple lines inside the hollow circle have to be connected with the pins represented by the simple lines inside the hollow circle and the pins represented by the crossed lines inside the hollow circle have to be connected with the pins represented by the crossed lines inside the hollow circle. Before connection, these points have to be escaped towards the boundary first as shown in Fig. 2.

It can be seen in the Fig. 2 that all the pins have been escaped to the boundary of pin arrays without any conflicts inside the pin array, but there is a conflict route in the intermediate area as shown in Fig. 3. In this situation, one of these routes will be routed on the same layer while the other will be left to be routed on the second layer as shown in Fig. 4. This shows that the basic problem is to escape the pins from inside of the pin array on the same layer and then connect these escaped pins by using minimum possible layers in the intermediate area. For this purpose, the pins will be escaped to the boundary in such a way so that conflicts are minimized in the intermediate area. For the sake of simplicity, routing is done only on a single layer. So the problem can be stated as:

“To simultaneously escape the pins from inside the pin arrays to the boundaries and connect the escaped pins while achieving 99.9% routability and minimizing the time required”.

Network flow approach

The problem formulated in the previous section was to escape the pins from inside the pin arrays to the boundary of pin arrays and then to connect them in the intermediate area. The components whose pins are to be connected are placed on a board in a manner which is shown in the Fig. 5. The square boxes and remaining points in the Fig. 5 represent the ICs and grid points for intermediate area routing respectively. The Objective is to connect these pins with each other by first escaping them from inside of the IC simultaneously and then connecting the escaped pins together. This issue is similar to the traffic flows in a network and hence, it can be mapped to a network flow problem. In the network, a node needs to communicate with another node and hence there is a need to establish a route between them. Similarly, the pins in our problem can be considered as nodes of a network the connection between them can be considered as a route. The purpose is to create a route from one node to another node i.e. connect two pins with each other. A grid is shown in Fig. 5 and this grid is similar to a network grid and there multiple nodes in that network in a mesh topology.

Different types of pins are shown in Fig. 6 with the help of circular points where the pins that need to be connected are shown with a hollow circle and crossed lines inside the circles. The filled circles show the intermediate nodes through which these pins can be connected to each other. In terms of the network flow, these cross lined hollow circles are considered as the source and destination nodes while the filled circles are considered as the intermediate nodes. The objective is to create a route from the source node towards the destination node by making use of the intermediate nodes. There can be multiple pins that need to be connected with each other and hence, there can be multiple source-destination pairs and these pairs are considered as flows in the network.

These pairs of pins can be mapped to a network flow. The immediate neighbors of a source and destination pin are also mapped to the neighboring network nodes. As there is a link between network nodes, this link is considered as the pin connection. The Table 1 shows how the mapping from the routing in a PCB to flows in a network is carried out. The terms related to PCB routing are mentioned in the PCB Routing column and their mapping to network flow is shown in the Network Flow column.

Addressing link based and node based routing issues

Memory consumption is the main issue with the link based and node based routing proposed in our earlier work (Ali, Zeeshan & Naveed, 2017). There are large number of the variables used in those approaches and as the number of grid points increase, the memory consumption also increases. These issues are solved by the dual model node based routing proposed in this paper which not only divides the total memory consumption between two models known as local routing and global routing but, also ensures the solution with unique routes. For a simple 10 × 10 grid, the number of variables used in the dual model node based routing can be calculated by using Algorithm 1. Local routing model of the dual model node based routing used 36 variables. The number of variables in the global routing model can be calculated a presented in Algorithm 2.

The total number of the variables in both models is 100 which is equal to the number of variables used in the node based routing proposed in our previous study (Ali, Zeeshan & Naveed, 2017) but, these variables are divided among two models and are solved separately. Hence there is no issue of memory consumption and the end to end route with uniqueness is also ensured by the dual model node based routing. The mathematical model and the related terminology of dual model node based routing is explained in the next section.

Terminology and mathematical model

The Table 2 shows the terminology that is helpful in understanding the dual model node based routing.

The local routing algorithm of the dual model node based routing is explained in Algorithm 3 and it uses the constraints which are detailed in Algorithm 3. A flowchart for Algorithm 3 is shown in Fig. S1.

Constraints for local routing model

The objective function of Local Routing Model is as follows:

$$min\sum _{\left(i,j\right)\epsilon SD}\sum _{\left(l,m\right)\epsilon P}{X}_{i,j,l,m}$$

subject to:

(1) $$X_{i,j,i,j}=1,\mathrm{\forall }\left(i,j\right)\epsilon LF$$

(2) $$\sum _{\left(l,m\right)\epsilon N\left(LF\right)}{X}_{i,j,l,m}=1,\mathrm{\forall }\left(i,j\right)\epsilon LF$$

The Eq. (1) makes sure that the starting point for a particular flow is selected. The Eq. (2) makes sure that one of the neighbors of that starting point must be selected. This is used in order to start the routing from source and keep it moving towards its neighbor.

These Eqs. (1) and (2) start the flow but do not make sure that it will continue towards the boundary points. We have used three equations for that. The Eqs. (3), (4) and (5) ensure the continuity of flow towards the boundary points and also make sure that a neighbor which is already selected, does not get selected again. This is used to make sure that flow does not go back towards source.

(3) $$2\times X_{i,j,l,m}\le \sum _{\left(a,b\right)\epsilon N\left(l,m\right)}{X}_{i,j,a,b},\mathrm{\forall }\left(i,j\right)\epsilon LF,\mathrm{\forall }\left(l,m\right)\epsilon CP-LF$$

(4) $$\sum _{\left(c,d\right)\epsilon N\left(l,m\right)}{X}_{a,b,c,d}\le 2,\mathrm{\forall }\left(a,b\right)\epsilon LF,\mathrm{\forall }\left(l,m\right)\epsilon CP$$

(5) $$\sum _{\left(l,m\right)\epsilon BP}{X}_{i,j,l,m}=1,\mathrm{\forall }\left(i,j\right)\epsilon LF$$

Now, we have the routed the source points towards the boundary points but we also need an equation that routes the same destination points to the boundary points. Therefore, we use the same equations for the destination points which were used for the source points. The Eqs. (6) and (7) make sure that the destination points of the flow are selected along with one of their neighbors. This is done to make sure that the route starts from destination point and move towards one of its neighbors.

(6) $$X_{a,b,a,b}=1,\mathrm{\forall }\left(i,j\right)\epsilon LF,\mathrm{\forall }\left(a,b\right)\epsilon D\left(LF\right)$$

(7) $$\sum _{\left(l,m\right)\epsilon N\left(a,b\right)}{X}_{a,b,l,m}=1,\mathrm{\forall }\left(i,j\right)\epsilon LF,\mathrm{\forall }\left(a,b\right)\epsilon D\left(LF\right)$$

The Eqs. (8), (9) and (10) and (11) ensure the continuity of flow of destination point towards the boundary points. The previously mentioned equations only selected the destination point and one of the neighbors but, these equations make sure that an already selected neighbor is not selected again and the route continues to flow towards the boundary points.

(8) $$2\times X_{i,j,l,m}\le \sum _{\left(a,b\right)\epsilon N\left(l,m\right)}{X}_{i,j,a,b},\mathrm{\forall }\left(l,m\right)\epsilon CP-D\left(LF\right),\mathrm{\forall }\left(i,j\right)\epsilon D\left(LF\right)$$

(9) $$\sum _{\left(c,d\right)\epsilon N\left(l,m\right)}{X}_{a,b,c,d}\le 2,\mathrm{\forall }\left(a,b\right)\epsilon D\left(LF\right),\mathrm{\forall }\left(l,m\right)\epsilon CP$$

(10) $$\sum _{\left(l,m\right)\epsilon BP}{X}_{a,b,l,m}=1,\mathrm{\forall }\left(a,b\right)\epsilon D\left(LF\right)$$

(11) $$\sum _{\left(i,j\right)\epsilon SD}{X}_{i,j,a,b},\mathrm{\forall }\left(i,j\right)\epsilon LF,\mathrm{\forall }\left(a,b\right)\epsilon CP$$

Constraints for global routing model

The global routing algorithm of the dual model node based routing is explained in Algorithm 4 and it uses the following objective function and constraints in Eqs. (12) & (13). A flowchart for Algorithm 4 is shown in Figs. S2.

objective function:

$$max\sum _{\left(i,j\right)\epsilon LF}\sum _{\left(c,d\right)\epsilon N\left(startx\left[i,j\right],starty\left[i,j\right]\right)}{Y}_{i,j,c,d}$$

The local routing model has selected the boundary points for both the source and destination points. The local routing model has provided these boundary points to the global routing model. Now, it is the responsibility of the global routing model to connect these boundary points together. The first step is to select these boundary points and the Eqs. (12) and (13) ensure that the boundary points provided by the local routing model are selected in the global routing model.

subject to:

(12) $$Y_{i,j,startx\left[i,j\right],starty\left[i,j\right]}=1,\mathrm{\forall }\left(i,j\right)\epsilon LF$$

(13) $$Y_{a,b,endx\left[a,b\right],endy\left[a,b\right]}=1,\mathrm{\forall }\left(a,b\right)\epsilon LF$$

After the selection of boundary points, the next step is to select one of the neighbors of the source boundary points and then continue the flow towards the destination boundary points. The Eqs. (14), (15) and (16) are used to ensure the continuity of the flow from source boundary point to destination boundary point.

(14) $$\sum _{\left(c,d\right)\epsilon N\left(startx\left[i,j\right],starty\left[i,j\right]\right)}{Y}_{a,b,c,d}\le 1,\mathrm{\forall }\left(a,b\right)\epsilon LF$$

$$2\times Y_{a,b,l,m}\le \sum _{\left(c,d\right)\epsilon N\left(l,m\right)}{Y}_{a,b,c,d},$$

(15) $$\mathrm{\forall }\left(a,b\right)\epsilon LF,\mathrm{\forall }\left(l,m\right)\epsilon BP-SDBP\left(LF\right)$$

(16) $$\sum _{\left(c,d\right)\epsilon N\left(l,m\right)}{Y}_{a,b,c,d}\le 2,\mathrm{\forall }\left(a,b\right)\epsilon LF,\mathrm{\forall }\left(l,m\right)\epsilon BP$$

There is a possibility that two or more than two flows will select a same point in their route. This possibility will cause the crossover and uniqueness of the routes will be affected. These chances of flows crossover in the second model is avoided by Eq. (17).

(17) $$\sum _{\left(i,j\right)\epsilon LF}{Y}_{i,j,a,b}\le 1,\mathrm{\forall }\left(a,b\right)\epsilon BP$$

The issues of memory consumption and the route uniqueness are solved by the dual model node based routing. Apart from that, very small time was consumed to find out the optimal path. In the next section, some results are included to support the models proposed.