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Developed in the 1980s Adaptive Solutions' CNAPS-1064 Digital Parallel Processor chip is a full [[Neurochip|neural network (NNW)]]. It was designed as a [[coprocessor]] to a host and has 64 sub-processors arranged in a [[Network topology|1D array]] and operating in a [[SIMD]] mode. Each sub-processor can emulate one or more neurons and multiple chips can be grouped together. At 25 MHz it is capable of 1.28 [[Multiply–accumulate operation|GMAC]].<ref name="Weems">[ftp://ftp.cs.umass.edu/pub/osl/papers/uPSurvey-TR-95-42.ps.Z ''Real-Time Computing: Implications for General Microprocessors''] Chip Weems, Steve Dropsho</ref>
After the presentation of the RN-100 (12 MHz) single neuron chip at Seattle 1991 [[Ricoh]] developed the multi-neuron chip RN-200. It had 16 neurons and 16 synapses per neuron. The chip has on-chip learning ability using a proprietary backdrop algorithm. It came in a 257-pin [[Pin grid array|PGA]] encapsulation and drew 3.0 W at a maximum. It was capable of 3
<ref name="Almeida2003">{{cite book
|author1=L. Almeida |author2=Luis B. Almeida |author3=S. Boverie |year = 2003
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|url = https://books.google.com/books?id=pDFdub32IdYC |isbn=9780080440101 }}</ref>
In
In 2013, the [[K computer]] was used to simulate a neural network of 1.73 billion neurons with a total of 10.4 trillion synapses (1% of the human brain). The simulation ran for 40 minutes to simulate 1 s of brain activity at a normal activity level (4.4 on average). The simulation required 1 Petabyte of storage.<ref name="CNET20130805">[http://www.cnet.com/news/fujitsu-supercomputer-simulates-1-second-of-brain-activity/ ''Fujitsu supercomputer simulates 1 second of brain activity''] Tim Hornyak, CNET, August 5, 2013</ref>
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