Wikipedia

14 nm process

(Redirected from 14 nm)
The 12 nm, 14 nm, and 16 nm fabrication nodes are discussed here.

The "14 nanometer process" refers to a marketing term for the MOSFET technology node that is the successor to the "22 nm" (or "20 nm") node. The "14 nm" was so named by the International Technology Roadmap for Semiconductors (ITRS). Until about 2011, the node following "22 nm" was expected to be "16 nm". All "14 nm" nodes use FinFET (fin field-effect transistor) technology, a type of multi-gate MOSFET technology that is a non-planar evolution of planar silicon CMOS technology.

Since at least 1997, "process nodes" have been named purely on a marketing basis, and have no relation to the dimensions on the integrated circuit;[1] neither gate length, metal pitch or gate pitch on a "14nm" device is fourteen nanometers.[2][3][4] For example, TSMC and Samsung's "10 nm" processes are somewhere between Intel's "14 nm" and "10 nm" processes in transistor density, and TSMC's "7 nm" processes are dimensionally similar to Intel's "10 nm" process.[5]

Samsung Electronics taped out a "14 nm" chip in 2014, before manufacturing "10 nm class" NAND flash chips in 2013.[dubious – discuss][clarification needed] The same year, SK Hynix began mass-production of "16 nm" NAND flash, and TSMC began "16 nm" FinFET production. The following year, Intel began shipping "14 nm" scale devices to consumers.[needs update]

History

edit

Background

edit

The resolutions of a "14 nm" device are difficult to achieve in a polymeric resist, even with electron beam lithography. In addition, the chemical effects of ionizing radiation also limit reliable resolution to about 30 nm, which is also achievable using current state-of-the-art immersion lithography. Hardmask materials and multiple patterning are required.

A more significant limitation comes from plasma damage to low-k materials. The extent of damage is typically 20 nm thick,[6] but can also go up to about 100 nm.[7] The damage sensitivity is expected to get worse as the low-k materials become more porous. For comparison, the atomic radius of an unconstrained silicon is 0.11 nm. Thus about 90 Si atoms would span the channel length, leading to substantial leakage.

Tela Innovations and Sequoia Design Systems developed a methodology allowing double exposure for the "16 nm"/"14 nm" node circa 2010.[8] Samsung and Synopsys had also, at that time, begun implementing double patterning in "22 nm" and "16 nm" design flows.[9] Mentor Graphics reported taping out "16 nm" test chips in 2010.[10][needs update] On January 17, 2011, IBM announced that they were teaming up with ARM to develop "14 nm" chip processing technology.[11][needs update]

On February 18, 2011, Intel announced that it would construct a new $5 billion semiconductor fabrication plant in Arizona, designed to manufacture chips using the "14 nm" manufacturing processes and leading-edge 300 mm wafers.[12][13] The new fabrication plant was to be named Fab 42, and construction was meant to start in the middle of 2011. Intel billed the new facility as "the most advanced, high-volume manufacturing facility in the world," and said it would come on line in 2013. Intel since decided to postpone opening this facility and instead upgrade its existing facilities to support 14-nm chips.[14][needs update] On May 17, 2011, Intel announced a roadmap for 2014 that included "14 nm" transistors for their Xeon, Core, and Atom product lines.[15][needs update]

Technology demos

edit

In the late 1990s, Hisamoto's Japanese team from Hitachi Central Research Laboratory began collaborating with an international team of researchers on further developing FinFET technology, including TSMC's Chenming Hu and various UC Berkeley researchers. In 1998, the team successfully fabricated devices down to a 17 nm process. They later developed a 15 nm FinFET process in 2001.[16] In 2002, an international team of researchers at UC Berkeley, including Shibly Ahmed (Bangladeshi), Scott Bell, Cyrus Tabery (Iranian), Jeffrey Bokor, David Kyser, Chenming Hu (Taiwan Semiconductor Manufacturing Company), and Tsu-Jae King Liu, demonstrated FinFET devices down to 10 nm gate length.[16][17]

In 2005, Toshiba demonstrated a 15 nm FinFET process, with a 15 nm gate length and 10 nm fin width, using a sidewall spacer process.[18] It had erstwhile been suggested in 2003 that for the 16 nm node, a logic transistor would have a gate length of about 5 nm.[19][needs update] In December 2007, Toshiba demonstrated a prototype memory unit that used 15-nanometre thin lines.[20]

In December 2009, National Nano Device Laboratories, owned by the Taiwanese government, produced a "16 nm" SRAM chip.[21][needs update]

In September 2011, Hynix announced the development of "15 nm" NAND cells.[22][needs update]

In December 2012, Samsung Electronics taped out a "14 nm" chip.[23][needs update]

In September 2013, Intel demonstrated an Ultrabook laptop that used a "14 nm" Broadwell CPU, and Intel CEO Brian Krzanich said, "[CPU] will be shipping by the end of this year."[24] However, as of February 2014, shipment had at time erstwhile been delayed further until Q4 2014.[25][needs update]

In August 2014, Intel announced details of the "14 nm" microarchitecture for its upcoming Core M processors, the first product to be manufactured on Intel's "14 nm" manufacturing process. The first systems based on the Core M processor were to become available in Q4 2014 — according to the press release. "Intel's 14 nanometer technology uses second-generation tri-gate transistors to deliver industry-leading performance, power, density and cost per transistor," said Mark Bohr, Intel senior fellow, Technology and Manufacturing Group, and director, Process Architecture and Integration.[26][needs update]

In 2018 a shortage of "14 nm" fab capacity was announced by Intel.[27][needs update]

Shipping devices

edit

In 2013, SK Hynix began mass-production of "16 nm" NAND flash,[28] TSMC began "16 nm" FinFET production,[29] and Samsung began "10 nm class" NAND flash production.[30]

On September 5, 2014, Intel launched the first three Broadwell-based processors that belonged to the low-TDP Core M family: Core M-5Y10, Core M-5Y10a, and Core M-5Y70.[31][needs update]

In February 2015, Samsung announced that their flagship smartphones, the Galaxy S6 and S6 Edge, would feature "14 nm" Exynos systems on chip (SoCs).[32][needs update]

On March 9, 2015, Apple Inc. released the "Early 2015" MacBook and MacBook Pro, which utilized "14 nm" Intel processors. Of note is the i7-5557U, which has Intel Iris Graphics 6100 and two cores running at 3.1 GHz, using only 28 watts.[33][34][needs update]

On September 25, 2015, Apple Inc. released the iPhone 6S & 6S Plus, which were erstwhile equipped with "desktop-class" A9 chips[35] that are fabricated in both "14 nm" by Samsung and "16 nm" by TSMC (Taiwan Semiconductor Manufacturing Company).[needs update]

In May 2016, Nvidia released its GeForce 10 series GPUs based on the Pascal architecture, which incorporates TSMC's "16 nm" FinFET technology and Samsung's "14 nm" FinFET technology.[36][37][needs update]

In June 2016, AMD released its Radeon RX 400 GPUs based on the Polaris architecture, which incorporated "14 nm" FinFET technology from Samsung. The technology had at that time been licensed to GlobalFoundries for dual sourcing.[38][needs update]

On August 2, 2016, Microsoft released the Xbox One S, which utilized "16 nm" by TSMC. [needs update]

On March 2, 2017, AMD released its Ryzen CPUs based on the Zen architecture, incorporating "14 nm" FinFET technology from Samsung which had erstwhile been licensed to GlobalFoundries for GlobalFoundries to build.[39][needs update]

The NEC SX-Aurora TSUBASA processor, introduced in October 2017,[40] used a "16 nm" FinFET process from TSMC and was designed for use with NEC SX supercomputers.[41][needs update]

On July 22, 2018, GlobalFoundries announced their "12 nm" Leading-Performance (12LP) process, based on a licensed 14LP process from Samsung.[42][needs update]

In September 2018, Nvidia released GPUs based on their Turing (microarchitecture), which were made on TSMC's "12 nm" process and had a transistor density of 24.67 million transistors per square millimeter.[43][needs update]

14 nm process nodes

edit
ITRS Logic Device
Ground Rules (2015) 		Samsung[a] TSMC[44] Intel GlobalFoundries[b] SMIC
Process name 16/14 nm 14LPE 14LPP 11LPP 16FF
(16 nm)		 16FF+
(16 nm)		 16FFC
(16 nm)		 12FFC
(12 nm) 		14 nm 14 nm + 14 nm ++ 14LPP[45]
(14 nm)		 12LP[46][47]
(12 nm)		 12LP+ 14 nm
Transistor density (MTr/mm2) Un­known 32.94[42] 54.38[42] 28.88[48] 33.8[49] 37.5[50][c]
44.67[52] 		30.59[42] 36.71[42] Un­known 30[53]
Transistor gate pitch (nm) 70 78 88 70 84 84 Un­known Un­known
Interconnect pitch (nm) 56 67 70 52 Un­known Un­known Un­known
Transistor fin pitch (nm) 42 49 45 42 48 Un­known Un­known
Transistor fin width (nm) 8 8 Un­known 8 Un­known Un­known Un­known
Transistor fin height (nm) 42 ~38 37 42 Un­known Un­known Un­known
Production year 2015 2014 Q4[54] 2016 Q1[55] 2018 H2[56] 2013 Q4 risk production
2014 production		 2015 Q3 2016 Q2 2017 2014 Q3[57] 2016 H2[58] 2017[59] 2016 2018 2020 Q3[60] 2019
  1. ^ Second-sourced to GlobalFoundries.
  2. ^ Based on Samsung's 14 nm process.
  3. ^ Intel uses this formula:[51]   #  

Lower numbers are better, except for transistor density, in which case the opposite is true.[61] Transistor gate pitch is also referred to as CPP (contacted poly pitch), and interconnect pitch is also referred to as MMP (minimum metal pitch).[62][63][64][65][66]

[67]

References

edit
  1. ^ "No More Nanometers – EEJournal". July 23, 2020.
  2. ^ Shukla, Priyank. "A Brief History of Process Node Evolution". design-reuse.com. Retrieved July 9, 2019.
  3. ^ Hruska, Joel. "14nm, 7nm, 5nm: How low can CMOS go? It depends if you ask the engineers or the economists..." ExtremeTech.
  4. ^ "Exclusive: Is Intel Really Starting To Lose Its Process Lead? 7nm Node Slated For Release in 2022". wccftech.com. September 10, 2016.
  5. ^ "Life at 10nm. (Or is it 7nm?) And 3nm - Views on Advanced Silicon Platforms". eejournal.com. March 12, 2018.
  6. ^ Richard, O.; et al. (2007). "Sidewall damage in silica-based low-k material induced by different patterning plasma processes studied by energy filtered and analytical scanning TEM". Microelectronic Engineering. 84 (3): 517–523. doi:10.1016/j.mee.2006.10.058.
  7. ^ Gross, T.; et al. (2008). "Detection of nanoscale etch and ash damage to nanoporous methyl silsesquioxane using electrostatic force microscopy". Microelectronic Engineering. 85 (2): 401–407. doi:10.1016/j.mee.2007.07.014.
  8. ^ Axelrad, V.; et al. (2010). Rieger, Michael L; Thiele, Joerg (eds.). "16nm with 193nm immersion lithography and double exposure". Proc. SPIE. Design for Manufacturability through Design-Process Integration IV. 7641: 764109. Bibcode:2010SPIE.7641E..09A. doi:10.1117/12.846677. S2CID 56158128.
  9. ^ Noh, M-S.; et al. (2010). Dusa, Mircea V; Conley, Will (eds.). "Implementing and validating double patterning in 22-nm to 16-nm product design and patterning flows". Proc. SPIE. Optical Microlithography XXIII. 7640: 76400S. Bibcode:2010SPIE.7640E..0SN. doi:10.1117/12.848194. S2CID 120545900.
  10. ^ "Mentor moves tools toward 16-nanometer". EETimes. August 23, 2010.
  11. ^ "IBM and ARM to Collaborate on Advanced Semiconductor Technology for Mobile Electronics". IBM Press release. January 17, 2011. Archived from the original on January 21, 2011.
  12. ^ "Intel to build fab for 14-nm chips". EE Times. Archived from the original on February 2, 2013. Retrieved February 22, 2011.
  13. ^ Update: Intel to build fab for 14-nm chips
  14. ^ "Intel shelves cutting-edge Arizona chip factory". Reuters. January 14, 2014.
  15. ^ "Implementing and validating double patterning in 22-nm to 16-nm product design and patterning flows". AnandTech. May 17, 2011.
  16. ^ a b Tsu-Jae King, Liu (June 11, 2012). "FinFET: History, Fundamentals and Future". University of California, Berkeley. Symposium on VLSI Technology Short Course. Retrieved July 9, 2019.
  17. ^ Ahmed, Shibly; Bell, Scott; Tabery, Cyrus; Bokor, Jeffrey; Kyser, David; Hu, Chenming; Liu, Tsu-Jae King; Yu, Bin; Chang, Leland (December 2002). "FinFET scaling to 10 nm gate length" (PDF). Digest. International Electron Devices Meeting. pp. 251–254. doi:10.1109/IEDM.2002.1175825. ISBN 0-7803-7462-2. S2CID 7106946. Archived from the original (PDF) on May 27, 2020. Retrieved December 10, 2019.
  18. ^ Kaneko, A; Yagashita, A; Yahashi, K; Kubota, T; et al. (2005). "Sidewall transfer process and selective gate sidewall spacer formation technology for sub-15nm FinFET with elevated source/drain extension". IEEE International Electron Devices Meeting (IEDM 2005). pp. 844–847. doi:10.1109/IEDM.2005.1609488.
  19. ^ "Intel scientists find wall for Moore's Law". ZDNet. December 1, 2003.
  20. ^ "15 Nanometre Memory Tested". The Inquirer. Archived from the original on December 13, 2007.{{cite web}}: CS1 maint: unfit URL (link)
  21. ^ "16nm SRAM produced – Taiwan Today". taiwantoday.tw. Archived from the original on March 20, 2016. Retrieved December 16, 2009.
  22. ^ Hübler, Arved; et al. (2011). "Printed Paper Photovoltaic Cells". Advanced Energy Materials. 1 (6): 1018–1022. Bibcode:2011AdEnM...1.1018H. doi:10.1002/aenm.201100394. S2CID 98247321.
  23. ^ "Samsung reveals its first 14nm FinFET test chip". Engadget. December 21, 2012.
  24. ^ "Intel reveals 14nm PC, declares Moore's Law 'alive and well'". The Register. September 10, 2013.
  25. ^ "Intel postpones Broadwell availability to 4Q14". Digitimes.com. February 12, 2014. Retrieved February 13, 2014.
  26. ^ "Intel Discloses Newest Microarchitecture and 14 Nanometer Manufacturing Process Technical Details". Intel. August 11, 2014.
  27. ^ "Intel Faces 14nm Shortage As CPU Prices Rise - ExtremeTech". www.extremetech.com.
  28. ^ "History: 2010s". SK Hynix. Archived from the original on May 17, 2021. Retrieved July 8, 2019.
  29. ^ "16/12nm Technology". TSMC. Retrieved June 30, 2019.
  30. ^ "Samsung Mass Producing 128Gb 3-bit MLC NAND Flash". Tom's Hardware. April 11, 2013. Archived from the original on June 21, 2019. Retrieved June 21, 2019.
  31. ^ Shvets, Anthony (September 7, 2014). "Intel launches first Broadwell processors". CPU World. Retrieved March 18, 2015.
  32. ^ "Samsung Announces Mass Production of Industry's First 14nm FinFET Mobile Application Processor". news.samsung.com.
  33. ^ "Apple MacBook Pro "Core i7" 3.1 13" Early 2015 Specs". EveryMac.com. 2015. Retrieved March 18, 2015.
  34. ^ "Intel Core i7-5557U specifications". CPU World. 2015. Retrieved March 18, 2015.
  35. ^ Vincent, James (September 9, 2015). "Apple's new A9 and A9X processors promise 'desktop-class performance'". The Verge. Retrieved August 27, 2017.
  36. ^ "Talks of foundry partnership between NVIDIA and Samsung (14nm) didn't succeed, and the GPU maker decided to revert to TSMC's 16nm process". Retrieved August 25, 2015.
  37. ^ "Samsung to Optical-Shrink NVIDIA "Pascal" to 14 nm". Retrieved August 13, 2016.
  38. ^ Smith, Ryan (July 28, 2016). "AMD Announces RX 470 & RX 460 Specifications; Shipping in Early August". Anandtech. Retrieved July 29, 2016.
  39. ^ "GlobalFoundries announces 14nm validation with AMD Zen silicon". ExtremeTech.
  40. ^ "NEC releases new high-end HPC product line, SX-Aurora TSUBASA". NEC. Retrieved March 21, 2018.
  41. ^ Cutress, Ian (August 21, 2018). "Hot Chips 2018: NEC Vector Processor Live Blog". AnandTech. Retrieved July 15, 2019.
  42. ^ a b c d e Schor, David (July 22, 2018). "VLSI 2018: GlobalFoundries 12nm Leading-Performance, 12LP". WikiChip Fuse. Retrieved May 31, 2019.
  43. ^ "NVIDIA GeForce RTX 30 Series & Ampere GPUs Further Detailed - GA102/GA104 GPU Specs & RTX 3090, RTX 3080, RTX 3070 Performance & Features Revealed". September 4, 2020.
  44. ^ "16/12nm Technology". TSMC. Retrieved November 12, 2022.
  45. ^ "PB14LPP-1.0" (PDF). GlobalFoundries. Archived from the original (PDF) on September 5, 2017. Retrieved November 28, 2022.
  46. ^ "PB12LP-1.1" (PDF). GlobalFoundries. Archived from the original (PDF) on December 27, 2018. Retrieved November 28, 2022.
  47. ^ Schor, David (July 22, 2018). "VLSI 2018: GlobalFoundries 12nm Leading-Performance, 12LP". WikiChip Fuse.
  48. ^ Schor, David (April 16, 2019). "TSMC Announces 6-Nanometer Process". WikiChip Fuse. Retrieved May 31, 2019.
  49. ^ "7nm vs 10nm vs 14nm: Fabrication Process - Tech Centurion". November 26, 2019.
  50. ^ "Intel Now Packs 100 Million Transistors in Each Square Millimeter". IEEE Spectrum: Technology, Engineering, and Science News. March 30, 2017. Retrieved November 14, 2018.
  51. ^ Bohr, Mark (March 28, 2017). "Let's Clear Up the Node Naming Mess". Intel Newsroom. Retrieved December 6, 2018.
  52. ^ "Intel's 10nm Cannon Lake and Core i3-8121U Deep Dive Review".
  53. ^ "SMIC-14nm". SIMC.
  54. ^ Frumusanu, Andrei. "The Samsung Exynos 7420 Deep Dive - Inside A Modern 14nm SoC". www.anandtech.com. Retrieved August 1, 2024.
  55. ^ Frumusanu, Andrei. "Samsung Announces Second-Gen 14nm Low Power Plus (14LPP) Process Now In Mass Production". www.anandtech.com. Retrieved August 1, 2024.
  56. ^ Shilov, Anton. "Samsung Details 11LPP Process Technology: 10 nm BEOL Meets 14 nm Elements". www.anandtech.com. Retrieved August 1, 2024.
  57. ^ Smith, Ryan. "Intel's 14nm Technology in Detail". www.anandtech.com. Retrieved August 1, 2024.
  58. ^ Cutress, Ian. "Intel Announces 7th Gen Kaby Lake: 14nm PLUS, Six Notebook SKUs, Desktop coming in January". www.anandtech.com. Retrieved August 1, 2024.
  59. ^ Howse, Brett. "Intel Announces 8th Generation Core "Coffee Lake" Desktop Processors: Six-core i7, Four-core i3, and Z370 Motherboards". www.anandtech.com. Retrieved August 1, 2024.
  60. ^ "GLOBALFOUNDRIES 12LP+ FinFET Solution Ready for Production". HPCwire. Retrieved August 1, 2024.
  61. ^ "Nanotechnology is expected to make transistors even smaller and chips correspondingly more powerful". Encyclopædia Britannica. December 22, 2017. Retrieved March 7, 2018.
  62. ^ "Intel 14nm Process Technology" (PDF).
  63. ^ "Samsung's 14 nm LPE FinFET transistors". Electronics EETimes. January 20, 2016. Retrieved February 17, 2017.
  64. ^ "14 nm lithography process - WikiChip". en.wikichip.org. Retrieved February 17, 2017.
  65. ^ "16 nm lithography process - WikiChip". en.wikichip.org. Retrieved February 17, 2017.
  66. ^ "International Technology Roadmap for Semiconductors 2.0 2015 Edition Executive Report" (PDF). Archived from the original (PDF) on October 2, 2016. Retrieved April 6, 2017.
  67. ^ Shilov, Anton. "SMIC Begins Volume Production of 14 nm FinFET Chips: China's First FinFET Line". AnandTech. Archived from the original on November 15, 2019. Retrieved November 16, 2019.
Preceded by
22 nm 		MOSFET manufacturing processes Succeeded by
10 nm
Retrieved from "https://en.wikipedia.org/w/index.php?title=14_nm_process&oldid=1242248133"