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File:NAND IEC.svg

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Original file (SVG file, nominally 100 × 50 pixels, file size: 5 KB)

Summary

Description IEC Symbol for a NAND Gate
Date 2/06/06
Source Own Drawing, made in Inkscape 0.43
Author jjbeard
Permission
(Reusing this file)		 PD

Licensing

Public domain I, the copyright holder of this work, release this work into the public domain. This applies worldwide.
In some countries this may not be legally possible; if so:
I grant anyone the right to use this work for any purpose, without any conditions, unless such conditions are required by law.

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File history

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Date/TimeThumbnailDimensionsUserComment
current18:12, 21 December 2008Thumbnail for version as of 18:12, 21 December 2008100 × 50 (5 KB)Inductiveload{{Information |Description= |Source= |Date= |Author= |Permission= |other_versions= }}
11:01, 19 December 2008Thumbnail for version as of 11:01, 19 December 2008100 × 50 (5 KB)Inductiveload{{Information |Description= |Source= |Date= |Author= |Permission= |other_versions= }}
04:39, 21 May 2007Thumbnail for version as of 04:39, 21 May 2007110 × 60 (6 KB)JjbeardMade square (according to IEEE 91-1984 2.2, they can be any height/width ratio. However, square seems to be the convetion used for single gates in this standard. Also made larger to allow use at 100% scaling and made the outline 3px for clarity. The text
04:36, 21 May 2007Thumbnail for version as of 04:36, 21 May 2007110 × 60 (4 KB)Jjbeard
12:38, 2 June 2006Thumbnail for version as of 12:38, 2 June 200650 × 30 (6 KB)Jjbeard{{Information |Description=IEC Symbol for a NAND Gate |Source=Own Drawing, made in Inkscape 0.43 |Date=2/06/06 |Author=jjbeard |Permission=PD |other_versions= }} Category:IEC_Logic_Gates

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