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== References ==
== References ==


* Heinrich, Joe. [ftp://ftp.sgi.com/sgi/doc/R4400/User_Manual/R4400_Uman_book_Ed2.pdf ''MIPS R4000 Microprocessor User's Manual''], Second Edition.
* Heinrich, Joe. [http://techpubs.sgi.com/library/manuals/2000/007-2489-001/pdf/007-2489-001.pdf ''MIPS R4000 Microprocessor User's Manual''], Second Edition.


{{MIPS microprocessors}}
{{MIPS microprocessors}}

Revision as of 18:42, 8 May 2009

The R4000 is microprocessor developed by MIPS Computer Systems that implemented the MIPS III instruction set architecture (ISA). Introduced in 1991, it was one of the first 64-bit microprocessors. In the early 1990s, when RISC microprocessors were expected to replace CISC microprocessors such as the Intel i486, the R4000 was selected to be the microprocessor of the Advanced Computing Environment (ACE), an industry standard that intended to define RISC platform, but ultimately failed due to a number of reasons.

There were three configurations of the R4000: the R4000PC, an entry-level model with no secondary cache; the R4000SC, a model with secondary cache but no multiprocessor capability; and the R4000MC, a model with secondary cache and support for the cache coherency protocols required by multiprocessor systems. The R4000PC was packaged in a 179-pin ceramic pin grid array (CPGA). The R4000SC and R4000MC were packaged in a 447-pin ceramic staggered pin grid array. The pin out of the R4000MC is different from the R4000SC, with some pins which are unused on the R4000SC used for signals to implement cache coherency on the R4000MC.

R4400

The R4400 was a further development of the R4000. It operated at higher clock frequencies of 150 to 200 MHz. The only major difference were larger primary caches, doubled to 16 KB each compared to 8 KB each. It was fabricated by IDT, LSI Logic, NEC Electronics, Performance Semiconductor, Siemens AG and Toshiba.

References