BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE, Pilani

FIRST SEMESTER 2024-2025

COURSE HANDOUT
Date: 01.08.2024

In addition to part I (General Handout for all courses appended to the Time table) this portion
gives further specific details regarding the course.

Course No: MEL G624

Course Title: Advanced VLSI Architectures
Instructor-in- Charge:
Prof. Subhendu Kumar Sahoo), [email protected] (Hyderabad Campus)
Prof. Upendra Mohan Bhatt, [email protected] (Pilani Campus)

1. Course Description:

The course explores advanced VLSI processor architectures, their implementation strategies
(microarchitectures) and associated memory hierarchies and their microarchitectures for high
performance system design. It also covers the various techniques utilized to leverage parallelism
at hardware, application and compiler levels. Students will gain an understanding of how (beyond
instruction-level parallelism) data-level parallelism, thread-level parallelism and task level parallelism
can be exploited to architect and implement different processing cores e.g.: Vector Processors, SIMD
processors and Multimedia processors, Graphical Processing Units (GPU) and General Purpose
Graphical Processing Units (GPGPU), Multi-core processors, Domain Specific Processors and
Memory hierarchy organizations for the above processors. The course also explores the
emerging research directions in VLSI processor design and system architectures.

2. Scope and Objective:

The objective of the course is to understand and gain an in-depth view of Advanced VLSI
Architectures: specifically to study various processor architectures, associated
microarchitectures and memory organizations that have evolved to exploit different types of
parallelisms to increase processor performance. The scope of the course covers the following in
detail:

(a) Study of advanced processor architectures and associated implementation techniques

(microarchitectures) and memory organization techniques

(b) This includes study of Vector, SIMD and GPU and Domain Specific architectures and
implementations

(c) Study of architectures and implementations that exploit thread-level parallelism and task
level parallelism via multi-processing (includes multicore processors)

(d) Study of memory hierarchy design for CPUs, vector processors, GPUs and application
domain specific processors
 BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE, Pilani

3. Text Book:

a). (T1) Computer Architecture: A Quantitative Approach, by John L. Hennessy and David A.
Patterson, Morgan Kaufmann, sixth edition, 2019.

4. Reference Books:

a). (R1) Research articles and reports: Details to be provided in the class

5. Course Plan:
Module Lect Topics to be covered Reference to Learning Outcome
Session Text

1 1-7 Introduction of the course and its positioning in Chapter-1 (T2) Learn:
the professional domain. Classification of Classification of
computers (from application point of view) and processors and
their design goals. Classification of computers computers from
from an architectural point of view. Review of application point of
technology and factors contributing to delay and view and
power consumption in computing / information architecture point of
processing. Speed and power implications of view.
computing / information processing architectures Also, speed and
and implementations. Power-delay trade-offs and power implications
low power techniques. Reliability, Availability, of their VLSI
Dependability issues Performance Metrics of implementations
processors/computers (06 Lectures)

2 8-14 Memory hierarchy design for high performance 2.2(T1), 3.1, 3.2, Learn: Complete
CPUs. (06 Lectures) 3.3(T2), Ref memory hierarchy

3 15-22 Leveraging data-level parallelism: Vector 2.1, Learn : DLP &

architectures and implementations; Multimedia 2.3(T1);3.4(T2), vector architectures
architectures and implementations. (08 Lectures) Ref

4 23-31 Graphical Processing Unit (GPU) and 2.4; 2.6; 2.10 Learn: GPUs
General Purpose GPU Architectures (08 (T1), Chapter 4
Lectures) (T2), Chapter 5 (
R1), Ref

5 32-39 Thread-level Parallelism and Multiprocessors: 4.6;4,7(T1) Learn: TLP &

centralized Shared memory architecture; Chapter 6 (T2), multicores
distributed shared-memory architecture; Ref
coherence, consistency and synchronization
issues and protocols.
(08 Lectures)

6 40-44 Dedicated hardware architectures and their Chapter 3 ( T1), Learn: ASIP, H/W
FPGA implementations. Application / Domain Ref accelerators, Domain
Specific Processor design and implementation. specific architectures
Recent (and research) architectures and their and research trends
implementations for machine learning,
machine vision, cognitive computing and real-
time big-data analytics. Seminars.
(05 Lectures)
 BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE, Pilani
Hyderabad Campus

6. Evaluation Scheme:

EC Evaluation Component
No.
Duration Marks Date and Time Nature of
(Weightage %) Component
(min)

1 Mid-Semester Exam 90 Min 25% As per Time table Closed Book

2 Assignments, NA 30% To be announced Open Book
Design Problems
3 Class room NA 10% Regular Open
participation and Book/Closed
evaluation Book
3 Comprehensive 180 Min 35% As per Time table Open
Exam Book/Closed
Book

* Details of the assignments will be announced later.

6. Chamber Consultation Hours: To be Announced

7. Make-up Policy:

Make Up for any component will be given only in genuine cases. In all cases prior intimation must be
given to IC.

9. Notices: Notices regarding the course will be displayed on Google classroom/CMS.

Academic Honesty and Integrity Policy: Academic honesty and integrity are to be maintained by
all the students throughout the semester and no type of academic dishonesty is acceptable

Instructor - in - charge