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Commit f54b637

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committedJun 9, 2024
fix simd_bitmask return type for non-power-of-two inputs, and add tests
1 parent d164925 commit f54b637

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2 files changed

+79
-15
lines changed

2 files changed

+79
-15
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‎compiler/rustc_codegen_llvm/src/intrinsic.rs

+4-3
Original file line numberDiff line numberDiff line change
@@ -1120,7 +1120,7 @@ fn generic_simd_intrinsic<'ll, 'tcx>(
11201120
let (len, _) = require_simd!(arg_tys[1], SimdArgument);
11211121

11221122
let expected_int_bits = (len.max(8) - 1).next_power_of_two();
1123-
let expected_bytes = len / 8 + ((len % 8 > 0) as u64);
1123+
let expected_bytes = len.div_ceil(8);
11241124

11251125
let mask_ty = arg_tys[0];
11261126
let mask = match mask_ty.kind() {
@@ -1386,8 +1386,8 @@ fn generic_simd_intrinsic<'ll, 'tcx>(
13861386
//
13871387
// The bit order of the result depends on the byte endianness, LSB-first for little
13881388
// endian and MSB-first for big endian.
1389-
let expected_int_bits = in_len.max(8);
1390-
let expected_bytes = expected_int_bits / 8 + ((expected_int_bits % 8 > 0) as u64);
1389+
let expected_int_bits = (in_len.max(8) - 1).next_power_of_two();
1390+
let expected_bytes = in_len.div_ceil(8);
13911391

13921392
// Integer vector <i{in_bitwidth} x in_len>:
13931393
let (i_xn, in_elem_bitwidth) = match in_elem.kind() {
@@ -1408,6 +1408,7 @@ fn generic_simd_intrinsic<'ll, 'tcx>(
14081408
};
14091409

14101410
// Shift the MSB to the right by "in_elem_bitwidth - 1" into the first bit position.
1411+
// FIXME: the docs say that valid inputs are `0` or `!0`, so the shift seems unnecessary.
14111412
let shift_indices =
14121413
vec![
14131414
bx.cx.const_int(bx.type_ix(in_elem_bitwidth), (in_elem_bitwidth - 1) as _);

‎tests/ui/simd/simd-bitmask.rs

+75-12
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,4 @@
11
//@run-pass
2-
//@ignore-endian-big behavior of simd_select_bitmask is endian-specific
32
#![feature(repr_simd, intrinsics)]
43

54
extern "rust-intrinsic" {
@@ -17,36 +16,100 @@ fn main() {
1716
let i: u8 = simd_bitmask(v);
1817
let a: [u8; 1] = simd_bitmask(v);
1918

20-
assert_eq!(i, 0b0101);
21-
assert_eq!(a, [0b0101]);
19+
if cfg!(target_endian = "little") {
20+
assert_eq!(i, 0b0101);
21+
assert_eq!(a, [0b0101]);
22+
} else {
23+
assert_eq!(i, 0b1010);
24+
assert_eq!(a, [0b1010]);
25+
}
2226

2327
let v = Simd::<i8, 16>([0, 0, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, -1, 0, -1, 0]);
2428
let i: u16 = simd_bitmask(v);
2529
let a: [u8; 2] = simd_bitmask(v);
2630

27-
assert_eq!(i, 0b0101000000001100);
28-
assert_eq!(a, [0b1100, 0b01010000]);
31+
if cfg!(target_endian = "little") {
32+
assert_eq!(i, 0b0101000000001100);
33+
assert_eq!(a, [0b00001100, 0b01010000]);
34+
} else {
35+
assert_eq!(i, 0b0011000000001010);
36+
assert_eq!(a, [0b00110000, 0b00001010]);
37+
}
2938
}
3039

3140
unsafe {
32-
let a = Simd::<i32, 8>([0, 1, 2, 3, 4, 5, 6, 7]);
33-
let b = Simd::<i32, 8>([8, 9, 10, 11, 12, 13, 14, 15]);
34-
let e = [0, 9, 2, 11, 12, 13, 14, 15];
41+
let a = Simd::<i32, 4>([0, 1, 2, 3]);
42+
let b = Simd::<i32, 4>([8, 9, 10, 11]);
43+
let e = [0, 9, 2, 11];
3544

36-
let r = simd_select_bitmask(0b0101u8, a, b);
45+
let mask = if cfg!(target_endian = "little") { 0b0101u8 } else { 0b1010u8 };
46+
let r = simd_select_bitmask(mask, a, b);
3747
assert_eq!(r.0, e);
3848

39-
let r = simd_select_bitmask([0b0101u8], a, b);
49+
let mask = if cfg!(target_endian = "little") { [0b0101u8] } else { [0b1010u8] };
50+
let r = simd_select_bitmask(mask, a, b);
4051
assert_eq!(r.0, e);
4152

4253
let a = Simd::<i32, 16>([0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]);
4354
let b = Simd::<i32, 16>([16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]);
4455
let e = [16, 17, 2, 3, 20, 21, 22, 23, 24, 25, 26, 27, 12, 29, 14, 31];
4556

46-
let r = simd_select_bitmask(0b0101000000001100u16, a, b);
57+
let mask = if cfg!(target_endian = "little") {
58+
0b0101000000001100u16
59+
} else {
60+
0b0011000000001010u16
61+
};
62+
let r = simd_select_bitmask(mask, a, b);
4763
assert_eq!(r.0, e);
4864

49-
let r = simd_select_bitmask([0b1100u8, 0b01010000u8], a, b);
65+
let mask = if cfg!(target_endian = "little") {
66+
[0b00001100u8, 0b01010000u8]
67+
} else {
68+
[0b00110000u8, 0b00001010u8]
69+
};
70+
let r = simd_select_bitmask(mask, a, b);
5071
assert_eq!(r.0, e);
5172
}
73+
74+
non_pow2();
75+
}
76+
77+
fn non_pow2() {
78+
// Non-power-of-2 multi-byte mask.
79+
#[repr(simd, packed)]
80+
#[allow(non_camel_case_types)]
81+
#[derive(Copy, Clone, Debug, PartialEq)]
82+
struct i32x10(i32, i32, i32, i32, i32, i32, i32, i32, i32, i32);
83+
impl i32x10 {
84+
fn splat(x: i32) -> Self {
85+
Self(x, x, x, x, x, x, x, x, x, x)
86+
}
87+
fn from_array(a: [i32; 10]) -> Self {
88+
unsafe { std::mem::transmute(a) }
89+
}
90+
}
91+
unsafe {
92+
let mask = i32x10::from_array([!0, !0, 0, !0, 0, 0, !0, 0, !0, 0]);
93+
let bitmask1: u16 = simd_bitmask(mask);
94+
let bitmask2: [u8; 2] = simd_bitmask(mask);
95+
if cfg!(target_endian = "little") {
96+
assert_eq!(bitmask1, 0b0101001011);
97+
assert_eq!(bitmask2, [0b01001011, 0b01]);
98+
} else {
99+
assert_eq!(bitmask1, 0b1101001010);
100+
assert_eq!(bitmask2, [0b11, 0b01001010]);
101+
}
102+
let selected1 = simd_select_bitmask::<u16, _>(
103+
if cfg!(target_endian = "little") { 0b0101001011 } else { 0b1101001010 },
104+
i32x10::splat(!0), // yes
105+
i32x10::splat(0), // no
106+
);
107+
let selected2 = simd_select_bitmask::<[u8; 2], _>(
108+
if cfg!(target_endian = "little") { [0b01001011, 0b01] } else { [0b11, 0b01001010] },
109+
i32x10::splat(!0), // yes
110+
i32x10::splat(0), // no
111+
);
112+
assert_eq!(selected1, mask);
113+
assert_eq!(selected2, selected1);
114+
}
52115
}

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