The 2-level FIFO architecture is proposed. It simplifies the design of the arbitration algorithm and gets better performance than other buffer architectures ...

The 2-level FIFO architecture is proposed. It simplifies the design of the arbitration algorithm and gets better performance than other buffer architectures ...

The 2-level FIFO architecture is proposed, which simplifies the design of the arbitration algorithm and gets better performance than other buffer architectures.

The 2-level FIFO architecture is proposed. It simplifies the design of the arbitration algorithm and gets better performance than other buffer architectures ...

The 2-level FIFO architecture is proposed. It simplifies the design of the arbitration algorithm and gets better performance than other buffer architectures ...

標題: 2-l.evel FIFO architecture design for switch fabrics in network-on-chip ; 作者: Huang, Po-Tsang · Hwang, Wei · 電子工程學系及電子研究所

Bibliographic details on 2-level FIFO architecture design for switch fabrics in network-on-chip.

The proposed two-level FIFO buffer architecture increases the utilities of the storage elements via the centralized buffer organization and reduces the area ...

Switch fabric architecture refers to the design and structure used in networking equipment, such as shared bus, shared memory, crossbars, and multistage ...

Architecture design principles for the integration of synchronization interfaces into Network-on-Chip switches. Article. Full-text available. Dec 2009.