This paper demonstrates a proof-of-concept of the low supply voltage circuit technique for high resolution cyclic analog-to-digital converters (ADCs).
Abstract— This paper demonstrates a proof-of-concept of the low supply voltage circuit technique for high resolution cyclic analog-to-digital converters ...
This paper presents the design of a low input (0.75 to 1.75V) and low power dissipation pipelined CMOS ADC. The 8 bits ADC consumes 78.3mW power at 2.5V supply ...
It consists of a 5-bit binary weighted capacitor array, a residue amplifier, a 6-bit signed Flash ADC and corresponding control logic.
A 0.8V 14bit 294kSPS non-binary cyclic ADC in 65nm SOTB CMOS technology. DOI PDF 被引用文献1件. Eiki Kayama · Kenta Mori · Maebou Taichi.
Other publications of authors with the same name ; A 0.8V 14bit 294kSPS non-binary cyclic ADC in 65nm SOTB CMOS technology.E. Kayama · K. Mori, M. Taichi, Y. Chen ...
A 0.8V 14bit 294kSPS non-binary cyclic ADC in 65nm SOTB CMOS technology · Eiki Kayama · Kenta Mori · Maebou Taichi · Yuanchi Chen · Hao San · Tatsuji Matsuura · Masao ...
A 0.8V 14bit 294kSPS non-binary cyclic ADC in 65nm SOTB CMOS technology. ... A 0.8V 14bit 62.5kSPS non-binary cyclic ADC using SOTB CMOS technology. ISPACS ...
A 0.8V 14bit 294kSPS non-binary cyclic ADC in 65nm SOTB CMOS technology, 2021 International Symposium on Intelligent Signal Processing and Communication ...
A 0.8V 14bit 294kSPS Non-Binary Cyclic ADC in 65nm SOTB CMOS Technology...38. Eiki Kayama, Kenta Mori, Taichi Maebou, Yuanchi Chen, Hao San, Tatsuji Matsuura ...