This paper presents an asynchronous SAR ADC design that combines several enhancement techniques to achieve high power efficiency.
An 8-bit asynchronous SAR ADC is designed with a 65 nm digital CMOS process using the proposed low power techniques. The sampling rate is set to 50 MS/s and the ...
An 8-bit successive approximation analog-to-digital converter (ADC) with small area and high power efficiency is presented in this paper.
Dec 1, 2012 · An 8-bit successive approximation analog-to-digital converter (ADC) with small area and high power efficiency is presented in this paper.
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A 15fJ/conversion-step 8-bit 50 MS/s asynchronous SAR ADC with efficient charge recycling technique. G Huang, P Lin. Microelectronics Journal 43 (12), 941-948, ...
This paper presents an energy-efficient charge-sharing SAR ADC design that targets for 1-V, 8-bit 40MS/s performance. By reconfiguring the networks for the ...
This paper presents an 8-bit asynchronous SAR ADC for flexible, low energy radios. The prototype in a 90nm CMOS technology achieves an ENOB of 7.7bit at a ...
This paper presents an 8-bit asynchronous SAR ADC for flexible, low energy radios that achieves an ENOB of 7.7bit at a sampling frequency of 10.24MS/s while ...
A 15fJ/conversion-step 8-bit 50MS/s asynchronous SAR ADC with efficient charge recycling technique. An 8-bit successive approximation analog-to-digital ...
A 15fJ/conversion-step 8-bit 50MS/s asynchronous SAR ADC with efficient charge recycling technique · Guanzhong Huang,Pingfen Lin +1 more. - 30 Nov 2012.