We propose a circuit technique for an 8T dual-port (DP) SRAM in order to screen degraded minimum operating voltage (V min ) due to the write/read disturb ...

Sep 1, 2011 · This circuitry allows us to screen the worst bit in an array that is conventionally obtained by a costly and time-consuming test procedure. For ...

To improve the operating margin or detecting margin less failure, test screening of the inherent disturb issues of 2RW DP SRAM have been discussed in advanced ...

This work designed and fabricated a 512-kb DP-SRAM macro using 28-nm low-power CMOS technology, and confirmed experimentally that the worst Vmin can be ...

A 28 nm Dual-Port SRAM Macro With Screening Circuitry Against Write-Read Disturb Failure Issues. IEEE J. Solid State Circuits 46(11): 2535-2544 (2011).

We demonstrate a 1-read/1-write two-port (2P) embedded static random access memory macro based on 8T SRAM bitcell with an effective scheme for design of ...

A 28-nm 1R1W Two-Port 8T SRAM Macro With Screening Circuitry Against Read Disturbance and Wordline Coupling Noise Failures.

Oct 22, 2024 · We demonstrate a 1-read/1-write two-port (2P) embedded static random access memory macro based on 8T SRAM bitcell with an effective scheme ...

Abstract: We demonstrate a 1-read/1-write two-port (2P) embedded static random access memory macro based on 8T SRAM bitcell with an effective scheme for ...

Abstract— This paper presents a low-energy and low-voltage. 64-kb 8T dual-port image memory in a 28-nm FD-SOI process technology. Our proposed SRAM adopts ...