A 28nm 157TOPS/W 446.9Kb/mm2 Compute-In-Memory SRAM Macro with Analog-Digital Hybrid Computing for Deep Neural Network Inference. Publisher: IEEE. Cite This.
Recent hybrid CIM designs try to solve those issues by combining analog and digital computation [3-4]. In this paper, we propose an energy- and area-efficient ...
... , Qiang Li. Page 4. A 28nm 157TOPS/W 446.9Kb/mm2 Compute-In-Memory SRAM Macro with Analog-Digital. Hybrid Computing for Deep Neural Network Inference ...
7-7: A 28nm 157TOPS/W 446.9Kb/mm2 Compute-In-Memory SRAM. Macro with Analog-Digital Hybrid Computing for Deep Neural. Network Inference. » Mr. Sangsu Jeong ...
This paper presents a digital compute-in-memory (CIM) macro that provides high-precision computation required for training deep neural networks and running ...
Missing: 157TOPS/ 446.9Kb/mm2
A 28nm 157TOPS/W 446.9Kb/mm2 Compute-In-Memory SRAM Macro with Analog-Digital Hybrid Computing for Deep Neural Network Inference.
May 10, 2021 · A 351TOPS/W and 372.4GOPS compute-in-memory SRAM macro in 7 nm FinFET. CMOS for machine-learning applications. In: Proceedings of IEEE ...
4 days ago · We present a hybrid analog/digital computing circuit to solve a selective harmonic minimization problem. The approach leverages favorable ...
Missing: 157TOPS/ 446.9Kb/mm2
A 28nm horizontal-weight-shift and vertical-feature-shift-based separate-wl 6t-sram computation-in-memory unit-macro for edge depthwise neural-networks. B Wang, ...
A 28nm 157TOPS/W 446.9Kb/mm2 Compute-In-Memory SRAM Macro with Analog-Digital Hybrid Computing for Deep Neural Network Inference. 出版者サイト 複写サービスで ...