Abstract: This paper describes a 32-KB two-read, one-write ported L0 cache for 4.5-GHz operation in 1.2-V 130-nm dual-V/sub TH/ CMOS technology.
Abstract—This paper describes a 32-kB two-read, one-write ported L0 cache for 4.5-GHz operation in 1.2-V 130-nm dual- TH. CMOS technology. The local bitline ...
This paper describes a 32 KB dual-ported L0 cache for 4.5 GHz operation in 1.2 V, 130 nm CMOS. The local bitline uses a Self Reverse Bias scheme to achieve ...
Apr 21, 2024 · This paper describes a 32-KB two-read, one-write ported L0 cache for 4.5-GHz operation in 1.2-V 130-nm dual-V<sub>TH</sub> CMOS technology.
Apr 16, 2002 · This paper describes a 32KB dual-ported L0 cache for 4.5GHz operation in 1.2V, 130nm CMOS. The local bitline uses a Self Reverse Bias scheme to ...
This paper presents a new technique, called X-calibration, to combat the phenomenon of excessive bit-line leakage current in an SRAM circuit.
“A 4.5-GHz 130-nm 32-kB L0 cache with a leakage-tolerant self reverse-bias bitline scheme”, IEEE J. Solid-State Circuits, 2003, 38(5), 755–761. Article ...
3) Self-Reverse Bias Bitline: The idea behind this technique is to invert the pre-charging value of the bitline so as to force a low-leakage state on the ...
A 4.5-GHz 130-nm 32-KB L0 cache with a leakage-tolerant self reverse-bias bitline scheme. Hsu, S. / Alvandpour, A. / Mathew, S. et al. | 2003. digital version.
A 4.5GHz 130nm 32KB L0 Cache with a Self Reverse Bias Scheme. Abstract, S. Hsu ... A Leakage-Tolerant Dynamic Register File Using Leakage Bypass with ...