In this paper, we have demonstrated current mode logic based novel 2:1 multiplexer featuring dual latch to be steered by either CLK or CLKBAR.

The rest of the paper is organized as follows: Section II discusses a brief review on the prior works of MUX and MUX-Latch circuits for SerDes applications.

In this paper, we have demonstrated current mode logic based novel 2:1 multiplexer featuring dual latch to be steered by either CLK or CLKBAR.

Nov 29, 2018 · MCML is a very popular logic to be used for multi-gigabit SerDes applications due to its simplicity and speed along with an extra benefit in ...

This work explores a novel configuration of multiplexer embedded with cross-coupled NMOS latch after integrating the Transmission Gate (TG) principle with the ...

Oct 7, 2024 · A 90nm Novel MUX-Dual Latch Design Approach for Gigascale Serializer Application. iNIS 2017: 210-214. [+][–]. Coauthor network. maximize. Note ...

A 90nm Novel MUX-Dual Latch Design Approach for Gigascale Serializer Application. M Das, A Majumder, AJ Mondal, BK Bhattacharyya. 2017 IEEE International ...

A 90nm Novel MUX-Dual Latch Design Approach for Gigascale Serializer Application. M Das, A Majumder, AJ Mondal, BK Bhattacharyya. 2017 IEEE International ...

A 90nm Novel MUX-Dual Latch Design Approach for Gigascale Serializer Application. 2017 IEEE International Symposium on Nanoelectronic and Information Systems ...

Majumder, A.J. Mondal, B.K. Bhattacharyya, “A 90nm Novel Mux-Dual Latch Design Approach for Gigascale Serializer Application”, 3rd IEEE International Symposium ...