A dynamic offset control technique that employs charge compensation by timing control is proposed for comparator design in scaled CMOS technology. The analysis has been verified by fabricating a 65 nm CMOS 1.2 V 1 GHz comparator that occupies 25 times 65 mum 2 and consumes 380 muW.
A dynamic offset control technique that employs charge compensation by timing control is proposed for comparator design in scaled CMOS technology. The analysis ...
SUMMARY. The accuracy of the comparator, which is often deter- mined by its offset, is essential for the resolution of the high performance.
The comparator is designed using differential input stages with regenerative S-R latch to achieve lower offset, lower power, higher speed and higher resolution.
Abstract-A principle of charge compensation approach for comparator offset control is analyzed. A dynamic offset control technique that employs charge ...
A dynamic offset control technique for comparator design in scaled CMOS technology. X. Zhu, Y. Chen, M. Kibune, Y. Tomita, T. Hamada, H. Tamura, ...
Abstract− A dynamic offset control technique that employs charge compensation by timing control is proposed for comparator design in scaled CMOS technology.
A low-offset two-stage dynamic comparator for parallel multi-channel processing that features small area overhead and low energy consumption is proposed
A high-speed dynamic comparator with preamplifier and automatic dc offset calibration in all stages is proposed in this paper.
Abstract—This paper presents a high resolution and wide range offset calibration technique for high resolution comparators.