A versatile low-jitter PLL in 90-nm CMOS for SerDes transmitter clocking.

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A versatile low-jitter PLL in 90-nm CMOS for SerDes transmitter clocking

A low-jitter charge-pump PLL is built in 90-nm CMOS for 1-10 Gb/s SerDes transmitter clocking. The PLL employs a programmable dual-path loop filter with ...

A Versatile 90-nm CMOS Charge-Pump PLL for SerDes ...

ieeexplore.ieee.org › iel5

Abstract—This paper presents a low-jitter charge-pump phase-locked loop (PLL) built in standard 90-nm CMOS for 1 to. 10 Gb/s wireline SerDes transmitter ...

[PDF] A Versatile Low-Jitter PLL in 90-nm CMOS for SerDes Transmitter ...

www.researchgate.net › links › A-v...

A low-jitter charge-pump PLL is built in 90-nm CMOS for 1–10. Gb/s SerDes transmitter clocking. The PLL employs a programma- ble dual-path loop filter with ...

(PDF) A versatile low-jitter PLL in 90-nm CMOS for SerDes transmitter ...

www.researchgate.net › ... › PLL

A low-jitter charge-pump PLL is built in 90-nm CMOS for 1-10 Gb/s SerDes transmitter clocking. The PLL employs a programmable dual-path loop filter with ...

[PDF] A versatile low-jitter PLL in 90-nm CMOS for SerDes ...

www.semanticscholar.org › paper

A low-jitter charge-pump PLL is built in 90-nm CMOS for 1-10 Gb/s SerDes transmitter clocking with programmable dual-path loop filter with integrating path ...

A Versatile 90-nm CMOS Charge-Pump PLL for SerDes ...

www.semanticscholar.org › paper › A-V...

This paper presents a low-jitter charge-pump phase-locked loop built in standard 90-nm CMOS for 1 to 10 Gb/s wireline SerDes transmitter clocking and design ...

A Versatile 90-nm CMOS Charge-Pump PLL for SerDes ...

ucl.primo.exlibrisgroup.com › fulldisplay

This paper presents a low-jitter charge-pump phase-locked loop (PLL) built in standard 90-nm CMOS for 1 to 10 Gb/s wireline SerDes transmitter clocking.

A versatile low-jitter PLL in 90-nm CMOS for SerDes transmitter ...

m.booksci.cn › literature

低抖动电荷泵锁相环是内置在90纳米CMOS 1-10 Gb/s SerDes发射机时钟。锁相环采用可编程双路环路滤波器，具有积分路径和新型无电阻比例路径，可独立控制和精确建模，可灵活 ...

A Low-Jitter and Low-Power CMOS PLL for Clock Multiplication

www.academia.edu › A_Low_Jitter_and...

A Versatile 90-nm CMOS Charge-Pump PLL for SerDes Transmitter Clocking · Tin ... Related topics. Low PowerLow Power ConsumptionDynamic LogicTRANSMITTERS ...

A 0.1–1.5 GHz, low jitter, area efficient PLL in 55-nm CMOS process

iopscience.iop.org › article › meta

This method could improve 3–6 dBc/Hz phase noise. The proposed PLL has been fabricated in 55 nm CMOS process with an integrated 16 pF metal–oxide–metal (MOM) ...