This talk will provide an overview of the Niagara 2 architecture, its physical implementation, and the challenges faced with designing a 65nm SoC ...

8 Sparc Cores, 4MB shared L2 cache; Supports concurrent execution of 64 threads. • >2x UltraSparc T1's throughput performance and performance/Watt. • >10x ...

8 Sparc Cores, 4MB shared L2 cache; Supports concurrent execution of 64 threads. • >2x UltraSparc T1's throughput performance and performance/Watt. • >10x ...

This talk will provide an overview of the Niagara 2 architecture, its physical implementation, and the challenges faced with designing a 65nm SoC microprocessor ...

This talk will provide an overview of the Niagara 2 architecture, its physical implementation, and the challenges faced with designing a 65nm SoC ...

This talk will provide an overview of the Niagara 2 architecture, its physical implementation, and the challenges faced with designing a 65nm SoC ...

Niagara2 has eight SPARC cores, each supporting concurrent execution of eight threads for 64 threads total. Each SPARC core has a floating point and graphics ...

Implementation of an 8-Core, 64-Thread, Power-Efficient SPARC Server on a Chip.

ISSCC 2007: An 8-core, 64-thread, 64-bit, power efficient SPARC SoC (Niagara2), U. Nawathe, M.Hassan, L. Warriner, K. Yen, B. Upputuri, D.Greenhill, A.Kumar ...

Apr 25, 2024 · An 8-core, 64-thread, 64-bit power efficient sparc soc (niagara2). ISPD 2007: 2. [c1]. view. electronic edition via DOI; unpaywalled version ...