Jan 28, 2011 · In this paper, we use a fully differential 8T SRAM that allows efficient bit-interleaving to achieve soft-error tolerance with conventional Error Correcting ...
In this paper, we use a fully differential 8T SRAM that allows efficient bit-interleaving to achieve soft-error tolerance with conventional Error Correcting.
To verify the technique, a 128 × 64-bit of the proposed SRAM has been implemented in a standard 65 nm/1 V CMOS process. Simulation results reaffirmed that the ...
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This chapter proposes a novel 8T-SRAM cell which is able to work at supply voltages lower than 200 mV through which the total power consumption and the ...
This article presents an 8T static random access memory (SRAM) macro with vertical read wordline (RWL) and selective dual split power (SDSP) lines techniques.
Oct 19, 2016 · The proposed SRAM cell improves write and read noise margin by at least 22% and 2.2X compared to the standard 6T-SRAM cell, respectively. Fur-.
In this paper, a novel highly stable 8T SRAM cell is proposed which eliminate any noise induction during read operation and keep the read SNM as high as 468 mV ...
Apr 20, 2024 · This paper investigates a low leakage power 8 T (LP8T) SRAM cell with high read and write stability. The proposed LP8T (PLP8T) SRAM cell has separate write and ...
We found experimentally that alpha particle soft error rate of 8T cells fabricated on a commercial 65 nm CMOS technology is 56% lower than a conventional 6T ...
Mar 14, 2024 · The experimental results show that the proposed 8T cell can provide approximately 1.28× improvement in read static noise margin (SNM) and 1.10× ...