An analytical model of memory-bound applications compiled with high level synthesis. Abstract: HLS tools simplify programming for FPGAs.

Our analytical model mainly requires static information and can be easily plugged into existing models to support memory-bound applications, or, even, ...

Mar 29, 2020 · High Level Synthesis tools improve the accessibility to FPGAs, but the optimization process is still time expensive due to the large compilation ...

Mar 29, 2020 · High Level Synthesis tools improve the accessibility to FPGAs, but the optimization process is still time expensive due to the large compilation ...

Apr 8, 2020 · An Analytical Model of Memory-Bound Applications Compiled with High Level Synthesis – Link for PDF Maria A. Dávila-Guzmán (Universidad de ...

HLS tools simplify programming for FPGAs, but generating highly tuned code still remains a challenge because CPU and GPU optimization techniques are not ...

As a design option to the well-established RTL design process, Accelerators can be designed using High-Level Synthesis. The abstraction level for the ...

We newly propose to estimate the communication performance for the DRAM-limited case based on dynamic prediction of the DRAM command patterns, ...

High Level Synthesis tools improve the accessibility to FPGAs, but the optimization process is still time expensive due to the large compilation time, between ...

The model has been validated with two DRAM technologies: DDR4 and HBM2, with a set of microbenchmarks and high performance computing applications showing an ...