May 16, 2014 · A DRAM device adopting CIDR has a small cache next to its I/O pads to replace accesses to the addresses that include the faulty cells with ones ...

We propose CIDR, a novel cache-inspired DRAM resilience architecture, which substantially reduces the area overhead of handling bit errors from these faulty ...

In this paper, we propose CIDR, a novel cache-inspired DRAM resilience architecture, which substantially reduces the area overhead of handling bit errors from ...

Compared to the conventional architecture relying on spare rows, CIDR lowers the area overhead of achieving equal failure rates over a wide range of single-bit ...

In this paper, we propose CIDR, a novel cache-inspired DRAM resilience architecture, which substantially reduces the area overhead of handling bit errors from ...

CiDRA is proposed, a cache-inspired DRAM resilience architecture, which substantially reduces the area and latency overheads of correcting bit errors on ...

Missing: CIDR: Area- Efficient Permanent

"CIDR: A Cache Inspired Area-Efficient DRAM Resilience Architecture against Permanent Faults". VOL. 14, NO. 1, JANUARY-JUNE 2015 Sweden: Graduate School of ...

CIDR: A Cache Inspired Area-Efficient DRAM Resilience Architecture against Permanent Faults. ... Lipasti: Adaptive Cache and Concurrency Allocation on GPGPUs.

In this paper, to improve error protection capacity of the tag bits in caches, power efficient cache design is proposed by using Superlative Standard Techniques.