A 10.3 Gb/s full-rate clock and data recovery circuit is designed and fabricated in a mature 45-GHz fT SiGe BiCMOS process based on injection-lock. To our ...
We present a 10.3Gb/s full-rate fully integrated injection-locked CDR circuit with a BER lower than 1e-12 over a 160MHz lock range. With a 33V supply, ...
Fig. 2 Schematic of the limiting amplifier - "Full-rate injection-locked 10.3Gb/s clock and data recovery circuit in a 45GHz-f/sub T/ SiGe process"
Missing: fT | Show results with:fT
... Injection Locking and Space Sampling for Multiaccess Networks · Full-rate injection-locked 10.3Gb/s clock and data recovery circuit in a 45GHz-fT SiGe process.
Duster, K.T. Kornegay, “A Full-Rate Injection-Locked. 10.3Gb/s Clock and Data Recovery Circuit in a 45GHz-fT SiGe Process,”.
Kornegay, “Full-rate injection-locked. 10.3Gb/s clock and data recovery circuit in a 45GHz-fT SiGe process,”. Proc. IEEE Custom Integrated Circuits Conference ...
An all-digital fully-synthesizable PVT-tolerant clock data recovery (CDR) architecture for wireline chip-to-chip interconnects is presented.
Abstract: In this paper, we demonstrate a novel 20-GSample/s burst-mode clock and data recovery. (BM-CDR) technique for optical multiaccess networks.
The BM-CDR incorporates an injection-locking method for clock recovery and a clock phase aligner employing space sampling with two multiphase clocks at 10 GHz ...
In this paper, a low-power Injection-Locked Clock and Data Recovery (ILCDR) using 28 nm FDSOI technology is presented. The back-gate auto-biasing of UTBB-FDSOI ...