In this study, we propose a high-throughput accelerator, called reconfigurable tiny neural network accelerator (ReTiNNA), for the bandwidth-limited system.
High-performance Reconfigurable DNN Accelerator on a Bandwidth-limited Embedded System · Author Picture Xianghong Hu. Guangdong University of Technology, China.
The proposed accelerator is the only implemented system on FGPA platform that can achieve multiple advantages: high-performanced, configurable, ...
Sep 5, 2023 · This survey article presents a comparative study of different deep NN (DNN) hardware accelerators implemented on customizable RISC-V processors.
Missing: Bandwidth- | Show results with:Bandwidth-
In order to solve this issue, in this study, we propose a high-throughput accelerator, called reconfigurable tiny neural-network accelerator (ReTiNNA) for the ...
High-performance Reconfigurable DNN Accelerator on a Bandwidth-limited Embedded System. Authors. Xianghong Hu · ORCID ID · Hongmin Huang · ORCID ID · Xueming Li ...
Eyeriss v2, a DNN accelerator architecture designed for running compact and sparse DNNs, is presented, which introduces a highly flexible on-chip network.
In this work, we introduce the first commercial hardware platform supporting high-degree sparsity acceleration up to 32 times -- S4. Combined with state-of-the- ...
Jun 27, 2023 · Such a DNN processor provides an energy-efficient set of convolutional accelerators supporting kernel compression, an on-chip reconfigurable ...
This work proposes a high-performance reconfigurable CNN accelerator architecture, called CASSANN-v2, which can achieve 1TOPS peak performance at 1GHz.
Missing: Bandwidth- | Show results with:Bandwidth-