A tagged architecture under constraints of a general purpose computer and a memory management strategy to achieve a high performance are discussed and then ...

This paper describes a high speed integrated. Prolog processor (IPP) which integrates the extended Warren's Prolog instructions, and its acceleration.

A tagged architecture under constraints of a general purpose computer and a memory management strategy to achieve a high performance are discussed and then an ...

An integrated Prolog processor (IPP) and its optimized compiler are now being developed and new functions such as indexing by the optimal argument and ...

Instruction Architecture for a High Performance Integrated Prolog Processor IPP ICLP, 1988. JICSLP 1988 · DBLP · Scholar. Full names. Links ISxN. @inproceedings ...

Ken-ichi Kurosawa, S. Yamaguchi, Shigeo Abe, Tadaaki Bandoh: Instruction Architecture for a High Performance Integrated Prolog Processor IPP.

Apr 25, 2024 · Ken-ichi Kurosawa, S. Yamaguchi, Shigeo Abe, Tadaaki Bandoh: Instruction Architecture for a High Performance Integrated Prolog Processor IPP ...

This paper discusses an optimal memory system to realize a high performance integrated Prolog processor, the IPP. First, the memory access characteristics ...

This paper presents extensions of a RISC processors's instruction set to enable a simplified and more efficient implementation of Prolog. The extensions are ...

Instruction Architecture for a High Performance Integrated Prolog Processor IPP. Автор: Kurosawa K. Yamaguchi S. Abe S. Bandoh T. Количество экземпляров: 1.