From the profiled results of MP3 algorithm on ARM processors it has been observed that, the synthesis filter bank in the audio decoder consumes maximum power.

From the profiled results of MP3 algorithm on ARM processors it has been observed that, the synthesis filter bank in the audio decoder consumes maximum power.

We developed an IEEE 754 single precision floating-point runtime reconfigurable architecture. The proposed architecture consumes less power at run time.

From the profiled results of MP3 algorithm on. ARM processors, it has been observed that the synthesis filter bank in the audio decoder consumes maximum power.

Jun 11, 2009 · We developed an IEEE 754 single precision floating-point runtime reconfigurable architecture. The proposed architecture consumes less power at run time.

Low power reconfigurable sub -band filter bank ASIC for MP3 decoder · Author(s): · B. P. Gangamamba · N. S. Murthy · P. Muralidhar.

In this paper low power techniques for MP3 audio decoder are used based on a phenomenon of zero-filled subbands. By our analysis, large part of subbands ...

Low power techniques for MP3 audio decoder using subband cut-off approach ... Low power reconfigurable sub -band filter bank ASIC for MP3 decoder · B. P. ...

Abstract. The sub-band filterbank is one of the most important modules which has the largest amount of calculation in MP3 decoding.

Low power reconfigurable sub-band filter bank ASIC for MP3 decoder · Low power reconfigurable pipelined architecture · MP3 decoder · Single precision multiplier.