Our experimental results using four-core multiprogramming workloads show that using x32 mini-ranks reduces memory power by 27.0% with 2.8% performance penalty ...

Oct 23, 2015 · Mini-rank: Adaptive DRAM architecture for improving memory power efficiency ... improve both DRAM performance and DRAM energy efficiency ...

Our experimental results using four-core multiprogramming workloads show that using x32 mini-ranks reduces memory power by 27.0% with 2.8% performance penalty ...

A novel idea called mini-rank for DDRx (DDR/DDR2/ DDR3) DRAMs is proposed, which uses a small bridge chip on each DRAM DIMM to break a conventional DRAM ...

The design dramatically reduces the memory power consumption with only a slight increase on the memory idle latency. It does not change the DDRx bus protocol ...

Nov 1, 2008 · Our experimental results using four-core multiprogramming workloads show that using x32 mini-ranks reduces memory power by 27.0% with 2.8% ...

A novel mini-rank architecture for DDRx memories to reduce memory power consumption by breaking each DRAM rank into multiple narrow mini-ranks and activating ...

We propose a novel mini-rank architecture for DDRx memories to reduce memory power consumption by breaking each DRAM rank into multiple narrow mini-ranks and ...

Mini-rank: Adaptive DRAM architecture for improving memory power efficiency. H Zheng, J Lin, Z Zhang, E Gorbatov, H David, Z Zhu. 2008 41st IEEE/ACM ...

Apr 25, 2024 · Mini-rank: Adaptive DRAM architecture for improving memory power efficiency. MICRO 2008: 210-221. [c6]. view. electronic edition via DOI ...