PDF | To implement convolutional neural networks (CNN) in hardware, the state-of-the-art CNN accelerators pipeline computation and data transfer stages.

This paper proposes a novel on-chip CNN accelerator for SR to optimize the CNN dataflow in the on- chip memory and develops a combined convolutional layer ...

Dec 5, 2022 · This article presents an energy-efficient accelerating system-on-chip (SoC) for super-resolution (SR) image reconstruction on a mobile platform.

In this paper, we propose a novel on-chip CNN accelerator for SR to optimize the CNN dataflow in the on-chip memory. First, the convolution loop optimization ...

We present eSRCNN, a framework that enables performing energy-efficient SR tasks on diverse embedded CNN accelerators by decreasing off-chip memory accesses.

Missing: Resolution. | Show results with:Resolution.

May 9, 2022 · This design accesses 8-bit input images, weights, and biases from off-chip DRAM and then stores them to the corresponding SRAM buffers. The ...

We present an all-on-chip super-resolution hardware ... Optimizing FPGA-based convolutional neural networks accelerator for image super-resolution.

This work presents eSRCNN, a framework that enables performing energy-efficient SR tasks on diverse embedded CNN accelerators by decreasing off-chip memory ...

Bibliographic details on On-Chip CNN Accelerator for Image Super-Resolution.