In this paper, we propose a technique for on-chip analog output response compaction in order to implement self-test capabilities in analog and mixed-signal ...

Abstract. In this paper; we propose a technique for on-chip analog output response compaction in order to implement self-test capabilities in analog and ...

In this paper, we propose a technique for on-chip analog output response compaction in order to implement self-test capabilities in analog and mixed-signal ...

Bibliographic details on On-chip analog output response compaction.

Abstract—In this paper, an X-tolerant multiple-input signature register (MISR) compaction methodology that compacts output responses containing unknown X ...

The “residue” voltage is then passed, as an analog input, to the second stage of the converter. The second stage is a 6-bit flash ADC that produces a “fine”.

This paper addresses the problem of test response compaction. In order to maximize compaction ratio, a single-output compactor based on a (n, n−1, m,

This paper concentrates on the 1-bit output compactors such as the XOR-tree depicted in Fig. 4, this case being the worst situation for an attacker. The ...

The ORA compacts the output responses of the CUT to the many test patterns produced by the TPG into a single Pass/Fail indication (usually a multi- ple-bit “ ...

This paper demonstrates a possibility to realize a simulation of testing strategy of high-resolution. Sigma-Delta modulator using MATLAB SIMULINK and. Xilinx ...