This paper presents a scalable parallel architecture, named Para Split, for high-performance packet classification. We propose a rule set partitioning algorithm ...

This paper presents a scalable parallel architecture, named Para Split, for high-performance packet classification, and proposes a rule set partitioning ...

This paper presents a scalable parallel architecture, named Para Split, for high-performance packet classification. We propose a rule set partitioning algorithm ...

This paper presents a scalable parallel architecture, named Para Split, for high-performance packet classification. We propose a rule set partitioning algorithm ...

Aug 21, 2012 · Each rule subset maps into a separate pipeline. Priority resolver to find the best matching rule. Dual-port BRAM for double performance ...

Abstract: This paper proposes a decision-tree-based linear multi-pipeline architecture on FPGA's for packet sorting. We reflect on the next-generation packet ...

This paper presents a scalable parallel architecture, named ParaSplit, for high-performance packet classification. We propose a rule set partitioning algorithm ...

2012 IEEE 20th Annual Symposium on High-Performance Interconnects. ParaSplit: A Scalable Architecture on FPGA for Terabit Packet Classification.

This paper presents a scalable parallel architecture, named Para Split, for high-performance packet classification. We propose a rule set partitioning algorithm ...

ParaSplit: A scalable architecture on FPGA for terabit packet classification ... A FPGA-based parallel architecture for scalable high-speed packet classification.