In this paper, we take SM2/SM3 algorithms as an example, to propose a brand new RISC-V compatible coprocessor design, named as ZigZag, aiming at easy usages in ...
This paper presents a high-performance SM2/3 coprocessor based on the RISC-V architecture. For the SM2 algorithm, a new parallel and pipelined design are ...
This research further expands the application of RISC-V in the IoT domain, offering new possibilities for performance optimization and feature enhancement ...
Point Multiplication ZigZag: An Optimized Co-Processor Architecture Design for SM2/3 Based on RISC-V. 2023, IEEE International Conference on Communications.
This paper proposes two different parallelization techniques to speedup the GF(p) elliptic curve multiplication in affine coordinates and the corresponding ...
Jan 13, 2024 · I'm curious if an in-order core and a co-processor can execute instructions in parallel when there is no data dependency between their tasks.
Point Multiplication ZigZag: An Optimized Co-Processor Architecture Design for SM2/3 Based on RISC-V.
[C17] Point Multiplication ZigZag: An Optimized Co-Processor Architecture Design for SM2/3 Based on RISC-V,. Yulong Chen, Yanjie Pei, Xiang Lu, Mengyao Shi.
Point Multiplication ZigZag: An Optimized Co-Processor Architecture Design for SM2/3 Based on RISC-V · Computer Science, Engineering. ICC 2023 - IEEE ...
Dec 5, 2021 · If Risc-V ends up popular, "fast carry" will be an implementation feature for the first time since the 1950s.
Missing: ZigZag: Co- SM2/