Basilio B. Fraguela

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Ramon DoalloComputer Architecture Group, CITIC, University of A CoruñaVerified email at udc.es
Diego AndradeUniversity of A CoruñaVerified email at udc.es
David PaduaProfessor Emeritus, University of Illinois at Urbana-ChampaignVerified email at illinois.edu
Maria GarzaranResearch assistant professor, University of Illinois at Urbana-ChampaignVerified email at uiuc.edu
Jia GuoGoogleVerified email at google.com
Guillermo L. Taboada, ORCID: 0000-0...Universidade da Coruña, Centro de investigación CITIC, Grupo de Arquitectura de ComputadoresVerified email at udc.es
A. GómezFundación Pública Gallega Centro Tecnológico de Supercomputación de GaliciaVerified email at cesga.es
María J. MartínUniversidade da Coruña, Centro de Investigación CITIC, Grupo de Arquitectura de ComputadoresVerified email at udc.es
Jose Carlos Mouriño GallegoCesgaVerified email at cesga.es
Pablo MontesinosAppleVerified email at apple.com
Zeki BozkusSenior Software Engineer, NVIDIA CorporationVerified email at nvidia.com
Dyer Rolán GarcíaXefe de Sección Xunta de GaliciaVerified email at udc.es
Margarita AmorUniversidade da CoruñaVerified email at udc.es
Roberto L. CastroUniversidade da CoruñaVerified email at udc.es
Jorge Fernández FabeiroSenior Applications Technician @ CESGAVerified email at cesga.es
Jose MoreiraResearch Staff Member, IBMVerified email at us.ibm.com
Jorge González-DomínguezCITIC, University of A CoruñaVerified email at udc.es
Manuel J. Castro DíazUniversidad de MálagaVerified email at uma.es
Josep TorrellasProfessor of Computer Science, University of Illinois Urbana-ChampaignVerified email at illinois.edu
Lawrence RauchwergerProfessor of Computer Science, University of Illinois at Urbana-ChampaignVerified email at illinois.edu

Basilio B. Fraguela

Universidade da Coruña, Centro de investigación CITIC, Depto. de Enxeñaría de Computadores

Verified email at udc.es - Homepage

Computer Architecture Parallel Programming HPC


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SESC simulator J Renau, B Fraguela, J Tuck, W Liu, M Prvulovic, L Ceze, S Sarangi, ... http://sesc.sourceforge.net, 2005	603*	2005
Programming for parallelism and locality with hierarchically tiled arrays G Bikshandi, J Guo, D Hoeflinger, G Almasi, BB Fraguela, MJ Garzarán, ... 11th ACM SIGPLAN Symposium on Principles and Practice of Parallel …, 2006	177	2006
Performance evaluation of mpi, upc and openmp on multicore architectures D Mallón, G Taboada, C Teijeiro, J Touriño, B Fraguela, A Gómez, ... Recent Advances in Parallel Virtual Machine and Message Passing Interface …, 2009	129	2009
Adaptive line placement with the set balancing cache D Rolán, BB Fraguela, R Doallo Proceedings of the 42nd Annual IEEE/ACM International Symposium on …, 2009	97	2009
Automatic analytical modeling for the estimation of cache misses BB Fraguela, R Doallo, EL Zapata 1999 International Conference on Parallel Architectures and Compilation …, 1999	86	1999
Programming the FlexRAM parallel intelligent memory system BB Fraguela, J Renau, P Feautrier, D Padua, J Torrellas ACM Sigplan Notices 38 (10), 49-60, 2003	62	2003
Programming with tiles J Guo, G Bikshandi, BB Fraguela, MJ Garzaran, D Padua Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of …, 2008	61	2008
Exploiting heterogeneous parallelism with the Heterogeneous Programming Library M Viñas, Z Bozkus, BB Fraguela Journal of Parallel and Distributed Computing 73 (12), 1627-1638, 2013	45	2013
The hierarchically tiled arrays programming approach BB Fraguela, J Guo, G Bikshandi, MJ Garzaran, G Almasi, J Moreira, ... Proceedings of the 7th workshop on Workshop on languages, compilers, and run …, 2004	43	2004
Probabilistic miss equations: Evaluating memory hierarchy performance BB Fraguela, R Doallo, EL Zapata IEEE Transactions on Computers 52 (3), 321-336, 2003	39	2003
A multi‐GPU shallow‐water simulation with transport of contaminants M Viñas, J Lobeiras, BB Fraguela, M Arenaz, M Amor, JA García, ... Concurrency and Computation: Practice and Experience 25 (8), 1153-1169, 2013	38	2013
Servet: A benchmark suite for autotuning on multicore clusters J González-Domínguez, GL Taboada, BB Fragüela, MJ Martín, J Tourino 2010 IEEE International Symposium on Parallel & Distributed Processing …, 2010	38	2010
Task-parallel versus data-parallel library-based programming in multicore systems D Andrade, BB Fraguela, J Brodman, D Padua 2009 17th euromicro international conference on parallel, distributed and …, 2009	37	2009
Writing productive stencil codes with overlapped tiling J Guo, G Bikshandi, BB Fraguela, D Padua Concurrency and Computation: Practice and Experience 21 (1), 25-39, 2009	33	2009
Optimal tile size selection guided by analytical models BB Fraguela, MG Carmueja, D Andrade International Conference on Parallel Computing (ParCo 2005) 10, 565-572, 2005	33	2005
A generic algorithm template for divide-and-conquer in multicore systems CH González, BB Fraguela 2010 IEEE 12th International Conference on High Performance Computing and …, 2010	32	2010
Automatic tuning of discrete fourier transforms driven by analytical modeling BB Fraguela, Y Voronenko, M Puschel 2009 18th International Conference on Parallel Architectures and Compilation …, 2009	32	2009
Automated and accurate cache behavior analysis for codes with irregular access patterns D Andrade, M Arenaz, BB Fraguela, J Tourino, R Doallo Concurrency and Computation: Practice and Experience 19 (18), 2407-2423, 2007	30	2007
Programming for locality and parallelism with hierarchically tiled arrays G Almasi, L De Rose, BB Fraguela, J Moreira, D Padua Languages and Compilers for Parallel Computing: 16th International Workshop …, 2004	29	2004
Modeling set associative caches behavior for irregular computations BB Fraguela, R Doallo, EL Zapata ACM SIGMETRICS Performance Evaluation Review 26 (1), 192-201, 1998	29	1998

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