| Proven correct monitors from PSL specifications K Morin-Allory, D Borrione Proceedings of the Design Automation & Test in Europe Conference 1, 1-6, 2006 | 89 | 2006 |
| Formal verification of VHDL descriptions in the Prevail environment DD Borrione, LV Pierre, AM Salem IEEE Design & Test of Computers 9 (2), 42-56, 1992 | 85 | 1992 |
| CONLAN report R Piloty, M Barbacci, D Borrione, D Dietmeyer Springer Science & Business Media, 1983 | 84 | 1983 |
| A method for symbolic verification of synchronous circuits T Filkorn Computer Hardware Description Languages and their Applications, 249-259, 1991 | 56 | 1991 |
| A generic model for formally verifying noc communication architectures: A case study D Borrione, A Helmy, L Pierre, J Schmaltz First International Symposium on Networks-on-Chip (NOCS'07), 127-136, 2007 | 51 | 2007 |
| Design error diagnosis in sequential circuits A Wahba, D Borrione Advanced Research Working Conference on Correct Hardware Design and …, 1995 | 42 | 1995 |
| A method for automatic design error location and correction in combinational logic circuits AM Wahba, D Borrione Journal of Electronic Testing 8, 113-127, 1996 | 41 | 1996 |
| The Conlan project: concepts, implementations, and applications R Piloty Computer 18 (02), 81-92, 1985 | 40 | 1985 |
| A formal approach to the verification of networks on chip D Borrione, A Helmy, L Pierre, J Schmaltz EURASIP Journal on Embedded Systems 2009, 1-14, 2009 | 38 | 2009 |
| CONLAN: a formal construction method for hardware description languages: basic principles R Piloty, M Barbacci, D Borrione, D Dietmeyer, F Hill, P Skelly Proceedings of the May 19-22, 1980, national computer conference, 209-217, 1980 | 36 | 1980 |
| PSL-based online monitoring of digital systems D Borrione, M Liu, P Ostier, L Fesquet Applications of Specification and Design Languages for SoCs: Selected papers …, 2006 | 33 | 2006 |
| A functional formalization of on chip communications J Schmaltz, D Borrione Formal Aspects of Computing 20, 241-258, 2008 | 32 | 2008 |
| Semantics of a verification-oriented subset of VHDL D Déharbe, D Borrione Advanced Research Working Conference on Correct Hardware Design and …, 1995 | 30 | 1995 |
| On-line assertion-based verification with proven correct monitors D Borrione, M Liu, K Morin-Allory, P Ostier, L Fesquet 2005 International Conference on Information and Communication Technology …, 2005 | 29 | 2005 |
| Towards a formal theory of on chip communications in the ACL2 logic J Schmaltz, D Borrione Proceedings of the sixth international workshop on the ACL2 theorem prover …, 2006 | 28 | 2006 |
| A functional approach to the formal specification of networks on chip J Schmaltz, D Borrione International Conference on Formal Methods in Computer-Aided Design, 52-66, 2004 | 27 | 2004 |
| A compositional model for the functional verification of high-level synthesis results D Borrione, J Dushina, L Pierre IEEE transactions on very large scale integration (VLSI) systems 8 (5), 526-530, 2000 | 27 | 2000 |
| A generic network on chip model J Schmaltz, D Borrione International Conference on Theorem Proving in Higher Order Logics, 310-325, 2005 | 26 | 2005 |
| An approach to the introduction of formal validation in an asynchronous circuit design flow D Borrione, M Boubekeur, E Dumitrescu, M Renaudin, JB Rigaud, ... 36th Annual Hawaii International Conference on System Sciences, 2003 …, 2003 | 26 | 2003 |
| A proof of correctness for the construction of property monitors K Morin-Allory, D Borrione Tenth IEEE International High-Level Design Validation and Test Workshop …, 2005 | 24 | 2005 |
Julien SchmaltzCGIVerified email at cgi.com
