An Ultra-Low-Power Tunable Bump Circuit using Source-Degenerated Differential Transconductor
Y He, M Choi, KK Kim, YB Kim - 2020 International SoC Design …, 2020 - ieeexplore.ieee.org
Y He, M Choi, KK Kim, YB Kim
2020 International SoC Design Conference (ISOCC), 2020•ieeexplore.ieee.orgIn this paper, we proposed a nano-power tunable bump circuit. It incorporates a novel
source-degenerated transconductor using pseudo-resistor as source resistor to control the
width of the bump. The presented circuit is simulated in Cadence using 180nm CMOS
process under 1.8 V power supply. The results show that the transconductance is tuned with
pseudo-resistor and the bump circuit can operate with wide voltage range from 0.3 V to 1.8
V. Also, this circuit is compact and only dissipates 16.7 nW power which makes it perfect for …
source-degenerated transconductor using pseudo-resistor as source resistor to control the
width of the bump. The presented circuit is simulated in Cadence using 180nm CMOS
process under 1.8 V power supply. The results show that the transconductance is tuned with
pseudo-resistor and the bump circuit can operate with wide voltage range from 0.3 V to 1.8
V. Also, this circuit is compact and only dissipates 16.7 nW power which makes it perfect for …
In this paper, we proposed a nano-power tunable bump circuit. It incorporates a novel source-degenerated transconductor using pseudo-resistor as source resistor to control the width of the bump. The presented circuit is simulated in Cadence using 180nm CMOS process under 1.8V power supply. The results show that the transconductance is tuned with pseudo-resistor and the bump circuit can operate with wide voltage range from 0.3V to 1.8V. Also, this circuit is compact and only dissipates 16.7nW power which makes it perfect for large-scale machine learning applications such as classifier and support vector machine.
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