Recent progress in EDA tools allows IC designs to be accurately verified with consequent
improvements in yield and performance through reduced guard bands. This paper will
present a tools perspective, including the primary effects such as HCI, NBTI and EM for
which EDA tools are available, types of tools (dynamic simulation vs. static rule checking)
and necessary reliability infrastructure and flows that have been working in practice. Finally,
developing areas and future opportunities will be addressed.

Reliability has recently become one of the most important things to worry about in
semiconductor design. In this age of miniaturization, particularly aggressive towards the
designer, there is a fierce pressure to deliver ever more performance out of shrinking design
margins, increasing role of secondary effects and integration density etc. In the past,
designers used to trade off reliability with safety margins, keeping in mind the anticipated
deterioration of the device over its intended lifetime. This all has changed due to very small …