5 V Supply Voltage Reference Based on the MOSFET ZTC Condition

D Cordova, P Toledo, H Klimach, S Bampi… - Proceedings of the 28th …, 2015 - dl.acm.org
Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015dl.acm.org
The continuous scaling of CMOS devices has required the consequent reduction of the
supply voltages. There is a need for analog and RF circuits able to operate under at supplies
lower than 0.5 V. This paper presents a voltage reference based on the MOSFET zero-
temperature condition (ZTC) that operates with a low 0.5 V supply. The circuit is composed
by a diode-connected MOS transistor operating near the ZTC condition that is biased by a
proportional-to-absolute-temperature (PTAT) current reference implemented with Schottky …
The continuous scaling of CMOS devices has required the consequent reduction of the supply voltages. There is a need for analog and RF circuits able to operate under at supplies lower than 0.5 V. This paper presents a voltage reference based on the MOSFET zero-temperature condition (ZTC) that operates with a low 0.5 V supply. The circuit is composed by a diode-connected MOS transistor operating near the ZTC condition that is biased by a proportional-to-absolute-temperature (PTAT) current reference implemented with Schottky-diodes. The ZTC condition is analysed using a continuous MOSFET model that is valid from weak to strong inversion and the circuit behaviour is described by theoretical expressions. Our reference circuit is designed for 3 versions: each with MOSFETs of different threshold voltage (standard-VT, low-VT, and zero-VT), all available in the 130 nm CMOS process used. These designs result in three different and very low reference voltages: 312, 237, and 51 mV. All 3 designed reference operate in the range of 0.45 to 1.2 V of supply voltages, consuming 1 uA of typical supply current. Post-layout simulations present a Temperature Coefficients (TCs) of 214, 372, and 953 ppm/°C in a temperature range from -55 to 125°C, respectively. Monte-Carlo simulations show the fabrication variability impact on the circuit performance. The voltage reference was designed in a 130 nm process and it uses 0.014 mm2 of silicon area.
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