This paper presents a 16-bit, 18-MSPS SAR ADC utilizing hybrid synchronous and asynchronous (HYSAS) timing control logic based on an on-chip delay-locked loop (DLL). The HYSAS scheme can provide a longer CDAC settling time than the synchronous and asynchronous SAR ADC. Therefore, the issue of incomplete settling or ringing in the DAC voltage for cases of either on-chip or off-chip reference voltage can be solved to a large extent. In addition, the foreground calibration of the CDAC's mismatch is performed with an FIR-BPF based LMS algorithm in an off-chip FPGA. Fabricated in 40-nm CMOS, the prototype ADC achieves 94.02-dB SFDR, and 75.98-dB SNDR for a 2.88-MHz input under 18-MSPS sampling rate.