A 30-GS/sec track and hold amplifier in 0.13-μm CMOS technology
S Shahramian, SP Voinigescu… - IEEE Custom Integrated …, 2006 - ieeexplore.ieee.org
S Shahramian, SP Voinigescu, AC Carusone
IEEE Custom Integrated Circuits Conference 2006, 2006•ieeexplore.ieee.orgA 30-GS/sec CMOS track and hold amplifier (THA) is designed and fabricated in a 0.13-μm
technology. The chip operates from a 1.8-V supply and consumes 270 mW. The THA
employs a low noise TIA input stage and a switched source follower (SSF) track and hold
block. The SSF topology overcomes the shortcomings of switched series transistors by
eliminating the use of a series switch all together. The measured single-ended S-parameters
show an input and output return loss of better than-10 dB up to 35 GHz and 7 GHz of …
technology. The chip operates from a 1.8-V supply and consumes 270 mW. The THA
employs a low noise TIA input stage and a switched source follower (SSF) track and hold
block. The SSF topology overcomes the shortcomings of switched series transistors by
eliminating the use of a series switch all together. The measured single-ended S-parameters
show an input and output return loss of better than-10 dB up to 35 GHz and 7 GHz of …
A 30-GS/sec CMOS track and hold amplifier (THA) is designed and fabricated in a 0.13-μm technology. The chip operates from a 1.8-V supply and consumes 270 mW. The THA employs a low noise TIA input stage and a switched source follower (SSF) track and hold block. The SSF topology overcomes the shortcomings of switched series transistors by eliminating the use of a series switch all together. The measured single-ended S-parameters show an input and output return loss of better than -10 dB up to 35 GHz and 7 GHz of bandwidth when the circuit is operated in track mode. The measured total harmonic distortion of the THA is better than -29 dB.
ieeexplore.ieee.org
Showing the best result for this search. See all results