This letter presents a D-band wideband power amplifier (PA) in a 65-nm CMOS process. By pole-tuning technique with T-type network, the PA achieves a flat gain response over a wide bandwidth. The high output power is achieved by combining the output power of two PA cells using a Y-type power combiner (YPC). The fabricated prototype achieves a peak gain of 11.5 dB at 115 GHz with a 3-dB bandwidth of more than 21 GHz and a fractional bandwidth of larger than 17.5%. At the operating frequency of 120 GHz, the saturation output power and the output P1dB are 13dBm and 8.7 dBm, respectively. The chip occupies a small silicon area of 0.59 mm2 including all testing pads with a core size of only 0.32 mm2.