A low power 64 Gb MLC NAND-flash memory in 15 nm CMOS technology
M Sako, Y Watanabe, T Nakajima… - IEEE Journal of Solid …, 2015 - ieeexplore.ieee.org
M Sako, Y Watanabe, T Nakajima, J Sato, K Muraoka, M Fujiu, F Kono, M Nakagawa…
IEEE Journal of Solid-State Circuits, 2015•ieeexplore.ieee.orgA 75 mm 2 low power 64 Gb MLC NAND flash memory capable of 30 MB/s program
throughput and 533 MB/s data transfer rate at 1.8 V supply voltage is developed in 15 nm
CMOS technology. 36% power reduction from 3.3 V design is achieved by a new pumping
scheme. New low current peak features reduce a multi-die concurrent programming peak by
65% for 4-die case, and an erase verifying peak by 40%, respectively. Nanoscale transistors
reducing bit-line discharge time by 70% is introduced to improve performance.
throughput and 533 MB/s data transfer rate at 1.8 V supply voltage is developed in 15 nm
CMOS technology. 36% power reduction from 3.3 V design is achieved by a new pumping
scheme. New low current peak features reduce a multi-die concurrent programming peak by
65% for 4-die case, and an erase verifying peak by 40%, respectively. Nanoscale transistors
reducing bit-line discharge time by 70% is introduced to improve performance.
A 75 mm 2 low power 64 Gb MLC NAND flash memory capable of 30 MB/s program throughput and 533 MB/s data transfer rate at 1.8 V supply voltage is developed in 15 nm CMOS technology. 36% power reduction from 3.3 V design is achieved by a new pumping scheme. New low current peak features reduce a multi-die concurrent programming peak by 65% for 4-die case, and an erase verifying peak by 40%, respectively. Nanoscale transistors reducing bit-line discharge time by 70% is introduced to improve performance.
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