A low-power multifunctional CMOS sensor node for an electronic facade
IEEE Transactions on Circuits and Systems I: Regular Papers, 2014•ieeexplore.ieee.org
In this paper, a low-power, multifunctional CMOS smart sensor node is designed for an
electronic facade, which provides an alternative solution to the concept of energy-efficient
responsive buildings. Various sensing capabilities, including light intensity sensing,
temperature sensing, motion tracking, and compressive image acquisition, are implemented
on the sensor node. An 80× 80 image pixel array is employed for motion tracking and
compressive image acquisition. Various operational modes are realized, including: 1) event …
electronic facade, which provides an alternative solution to the concept of energy-efficient
responsive buildings. Various sensing capabilities, including light intensity sensing,
temperature sensing, motion tracking, and compressive image acquisition, are implemented
on the sensor node. An 80× 80 image pixel array is employed for motion tracking and
compressive image acquisition. Various operational modes are realized, including: 1) event …
In this paper, a low-power, multifunctional CMOS smart sensor node is designed for an electronic facade, which provides an alternative solution to the concept of energy-efficient responsive buildings. Various sensing capabilities, including light intensity sensing, temperature sensing, motion tracking, and compressive image acquisition, are implemented on the sensor node. An 80 × 80 image pixel array is employed for motion tracking and compressive image acquisition. Various operational modes are realized, including: 1) event generation mode; 2) motion tracking mode; and 3) video output mode in full-resolution or compressed by the region of interest (ROI). A low-power, high-throughput motion detection algorithm is proposed in this paper. The power consumption of the proposed work is modeled, analyzed, and compared with traditional motion detection methods. According to numerical analysis, the throughput can be increased by 45% while using the proposed design instead of traditional temporal differential motion tracking methods with simislar power consumption. The proposed algorithm is realized by a pixel-level focal-plane motion detection unit, consisting of switched-capacitor circuit, analog memory, and dual-threshold comparator. The proposed design was fabricated in 0.5 μm 3M2P standard CMOS technology, occupying 3×3 mm2 silicon area. The total power consumption is 17 μW, while the pixel array is performing motion tracking with a frame rate of 30 fps and a supply voltage of 3.3 V.
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