Due to a variety of limitations on the system-on-chip (SoC), the microelectronics industry is now facing challenges and making slow progress in recent years. With architecture design and advanced packaging advantages, chiplet heterogeneous integration (CHI) systems have become a promising solution to long-lasting hardship. However, high power consumption in CHI systems generates massive heat and makes thermal design a demanding task. Therefore, an accurate tool for thermal simulation is indispensable in the design flow. In this article, a multiscale anisotropic thermal model is proposed for the CHI systems. It considers the feature-scale thermal conductivities of different materials to predict the package-scale steady-state temperature fields. Specifically, the local material composition and thermal conductivity of redistribution layers (RDLs) are extracted from design layout files by constructing an equivalent thermal conductivity algorithm of local feature structures. As for through silicon via (TSV) and bump arrays, the anisotropic distributions of thermal conductivity can also be derived with equivalent algorithms. Other structures are considered homogeneous blocks to significantly reduce the computational expense without losing the generality of the proposed model. Compared with the previous isotropic thermal model of CHI systems, the present multiscale anisotropic thermal model is proven to make temperature prediction and hotspot detection more reliable. With this tool, the reliability problems that are unpredictable and obscure for isotropic thermal models can be identified in advance, and more reasonable design space can be explored in the design flow of the CHI systems.