A subsampling radio architecture for ultrawideband communications
SWM Chen, RW Brodersen - IEEE transactions on signal …, 2007 - ieeexplore.ieee.org
SWM Chen, RW Brodersen
IEEE transactions on signal processing, 2007•ieeexplore.ieee.orgAn impulse radio architecture utilizing a simple analog front end along with digital complex
signal processing is proposed to allow a low complexity implementation of a 3.1-10.6 GHz
ultrawideband (UWB) radio. The proposed system transmits passband pulses using a pulser
and antenna, and the receiver front-end downconverts the signal frequency via
subsampling, thus, requiring substantially less hardware than the existing direct conversion
approach. After the analog-to-digital converter (ADC), the signal is projected into complex …
signal processing is proposed to allow a low complexity implementation of a 3.1-10.6 GHz
ultrawideband (UWB) radio. The proposed system transmits passband pulses using a pulser
and antenna, and the receiver front-end downconverts the signal frequency via
subsampling, thus, requiring substantially less hardware than the existing direct conversion
approach. After the analog-to-digital converter (ADC), the signal is projected into complex …
An impulse radio architecture utilizing a simple analog front end along with digital complex signal processing is proposed to allow a low complexity implementation of a 3.1-10.6 GHz ultrawideband (UWB) radio. The proposed system transmits passband pulses using a pulser and antenna, and the receiver front-end downconverts the signal frequency via subsampling, thus, requiring substantially less hardware than the existing direct conversion approach. After the analog-to-digital converter (ADC), the signal is projected into complex signal domain to perform matched filtering to not only mitigate the timing sensitivity induced by analog circuit impairment, but also extract the fine time resolution provided by the wideband nature of a UWB signal. The performance and potential usages of these complex signal processing blocks are solved and compared with different complex signal transformations. Based on the proposed architecture, the system specifications and implementation issues are further analyzed and emulated by system-level simulations with measured signal and noise. The subsampling ADC is considered as the most challenging circuit block and has recently been proven with a low-power low-cost fully integrated CMOS solution. Finally, a radio prototype built with discrete components is used for proof of concept.
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